Abstract: The embodiments herein describe a communication protocol (which can be implemented in hardware or software) that provides efficient recover packet loss and can transit large messages in a complex network environment. In one embodiment, each data packet contains an encoded universal sequence which is unique across the sends, which enables cross-sender loss recovery. A receiver can include a transmission control module that controls the receiving buffer and maintains the buffer status and the sender's status. The transmission control module stores incoming packets to the correct position in the receiving buffer and generates acknowledgement notifications. The transmission control module also handles packet loss and out-of-order receiving of the packets containing the transactions.

Abstract: A simulation framework is capable modeling a hardware implementation of a reference software system using models specified in different computer-readable languages. The models correspond to different ones of a plurality of subsystems of the hardware implementation. Input data is provided to a first simulator configured to simulate a first model of a first subsystem of the modeled hardware implementation. The input data is captured from execution of the reference software system. The first simulator executing the first model generates a first data file specifying output of the first subsystem. The first data file specifies intermediate data of the modeled hardware implementation. The first data file is provided to a second simulator configured to simulate a second model of a second subsystem of the modeled hardware implementation. The second simulator executing the second model generates a second data file specifying output of the second subsystem.

Abstract: Embodiments herein describe a hardware accelerator for a blockchain node. The hardware accelerator is used to perform a validation operation to validate one or more transactions before those transactions are committed to a ledger of a blockchain. The embodiments herein describe an out-of-order validation scheme where a collector is used to collect validated transactions out of order. Thus, if a validation pipeline has finished validating a later transaction before another validation pipeline has finished validating an earlier transaction, the pipeline can nonetheless send its results to the collector and retrieve another transaction from a scheduler. In this manner, the downtime for the validation pipelines is reduced or eliminated.

Abstract: Embodiments herein describe a hardware accelerator for a blockchain node. The hardware accelerator is used to perform a validation operation to validate one or more transactions before those transactions are committed to a ledger of a blockchain. The embodiments herein describe a scheduler for assigning validation engines to the transactions in response to the number of endorsements in the transactions.

Abstract: Embodiments herein describe a hardware accelerator for a blockchain node. The hardware accelerator is used to perform a validation operation to validate one or more transactions before those transactions are committed to a ledger of a blockchain. The blockchain may include multiple peer-nodes, each of which contains standard software running on a server or container. Instead of validating a block of transactions using software, the hardware accelerator can validate the transactions in a fraction of the time. The peer-node software then gathers the validation results from the hardware accelerator and combines the results with received block data to derive the block which is committed to the stored ledger.

Abstract: Embodiments herein describe a hardware accelerator (e.g., a network acceleration engine) for a blockchain machine or node. The hardware accelerator parses packets containing separate components of a block of transactions to generate data to perform a validation process. To avoid the latency that comes with using software, the embodiments herein describe a protocol processor in the hardware accelerator that parses the packets and prepares the data so it can be consumed by downstream components in the accelerator without software intervention. These downstream components can then perform a validation operation to validate one or more transactions before those transactions are committed (i.e., added) to a ledger of a permissioned blockchain.

Abstract: Embodiments herein describe a hardware accelerator (e.g., a network acceleration engine) for a blockchain machine or node. The hardware accelerator parses packets containing separate components of a block of transactions to generate data to perform a validation process. To avoid the latency that comes with using software, the embodiments herein describe a protocol processor in the hardware accelerator that parses the packets and prepares the data so it can be consumed by downstream components in the accelerator without software intervention. These downstream components can then perform a validation operation to validate one or more transactions before those transactions are committed (i.e., added) to a ledger of a permissioned blockchain.

Abstract: Embodiments herein describe a hardware accelerator for a blockchain node. The hardware accelerator is used to perform a validation operation to validate one or more transactions before those transactions are committed to a ledger of a blockchain. The blockchain may include multiple peer-nodes, each of which contains standard software running on a server or container. Instead of validating a block of transactions using software, the hardware accelerator can validate the transactions in a fraction of the time. The peer-node software then gathers the validation results from the hardware accelerator and combines the results with received block data to derive the block which is committed to the stored ledger.

Abstract: An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.

Abstract: Embodiments herein describe techniques for executing VMs on hosts that include an accelerator. The hosts can use the accelerators to perform specialized tasks such as floating-point arithmetic, encryption, image processing, etc. Moreover, VMs can be migrated between hosts. To do so, the state of the processor is saved on the current host thereby saving the state of the VM. For example, by saving the processor state, once the data corresponding to the VM is loaded into a destination host, the processor can be initialized to the saved state in order to resume the VM. In addition to saving the processor state, the embodiments herein save the state of the accelerator on a FPGA. That is, unlike previous systems where tasks executed by the accelerator are discarded when migrating the VM, the state of the accelerator can be saved and used to initialize an FPGA accelerator in the destination host.

Abstract: An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.

Abstract: An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.

Abstract: An apparatus can include a read data mover circuit adapted to fetch a portion of data for each of a plurality of read channels. The read data mover circuit is adapted to output, to an accelerator circuit, a plurality of bits of data for each of the plurality of read channels concurrently as first streamed data. The apparatus can include a controller configured to control operation of the read data mover circuit. In another aspect, the apparatus can include a write data mover circuit adapted to receive second streamed data from the accelerator circuit and output the second streamed data in a different format. The controller may be configured to control operation of the write data mover circuit.

Abstract: An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.

Abstract: Embodiments herein describe techniques for executing VMs on hosts that include an accelerator. The hosts can use the accelerators to perform specialized tasks such as floating-point arithmetic, encryption, image processing, etc. Moreover, VMs can be migrated between hosts. To do so, the state of the processor is saved on the current host thereby saving the state of the VM. For example, by saving the processor state, once the data corresponding to the VM is loaded into a destination host, the processor can be initialized to the saved state in order to resume the VM. In addition to saving the processor state, the embodiments herein save the state of the accelerator on a FPGA. That is, unlike previous systems where tasks executed by the accelerator are discarded when migrating the VM, the state of the accelerator can be saved and used to initialize an FPGA accelerator in the destination host.

Abstract: Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.

Abstract: In an example implementation, a method is provided for compiling an HLL source file including function calls to one or more hardware accelerated functions. Function calls in the HLL source file to hardware accelerated functions are identified and grouped into a plurality of subsets for exclusive implementation in programmable logic resources. Sets of configuration data are generated for configuration of the programmable logic resources to implement hardware accelerated functions for the respective subsets of function calls. An interface manager is generated and the identified function calls are replaced with interface code configured to communicate with the interface manager. The interface manager manages configuration of the programmable logic resources to switch between the sets of configuration data to implement hardware accelerated functions for different ones of the subsets.

Abstract: Implementing a system-on-chip (SOC) design specified as a high level programming language (HLL) application may include querying, using a computer, a platform description to determine an available interface of a platform for a target integrated circuit and generating, using the computer, hardware for a function of the HLL application marked for hardware acceleration and hardware coupling the marked function with the available interface of the platform. Implementing the SOC design may also include modifying, using the computer, the HLL application with program code configured to access the generated hardware for the marked function and building, using the computer, the hardware and the software of the SOC design.

Abstract: A multi-processor system with dynamic power optimization for an integrated circuit and methods thereof are described. An input rate control signal is generated responsive to at least one input data stream. An output rate control signal is generated responsive to an output of the plurality of processors. The input rate control signal and the output rate control signal are monitored. The at least one input data stream is partitioned in response to the input rate control signal. The partitioned data is distributed to at least a portion of the plurality of processors. The plurality of processors is operated in a plurality of modes responsive to the monitoring.

Abstract: A method and apparatus for adaptively tuning an integrated circuit are disclosed. For example, an integrated circuit (IC) comprises a monitored path comprising circuit elements operating on a clock signal, where a last circuit element of the circuit elements comprises a first flip flop. The IC also comprises a second flip flop operating on an early clock signal, where the early clock signal is phase shifted from the clock signal, and where the second flip flop is coupled to the monitored path prior to the last circuit element. The IC also comprises a transition detection module for detecting when an output from the first flip flop toggles, and an error prediction module to detect a potential error on the monitored path. The IC comprises a controller that is configured to scale a voltage or a frequency of the IC.