Patents by Inventor Sundararajarao Mohan

Sundararajarao Mohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200161247
    Abstract: An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.
    Type: Application
    Filed: January 27, 2020
    Publication date: May 21, 2020
    Inventors: Austin H. LESEA, Sundararajarao MOHAN, Stephen M. TRIMBERGER
  • Patent number: 10573598
    Abstract: An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: February 25, 2020
    Assignee: XILINX, INC.
    Inventors: Austin H. Lesea, Sundararajarao Mohan, Stephen M. Trimberger
  • Patent number: 10474599
    Abstract: An apparatus can include a read data mover circuit adapted to fetch a portion of data for each of a plurality of read channels. The read data mover circuit is adapted to output, to an accelerator circuit, a plurality of bits of data for each of the plurality of read channels concurrently as first streamed data. The apparatus can include a controller configured to control operation of the read data mover circuit. In another aspect, the apparatus can include a write data mover circuit adapted to receive second streamed data from the accelerator circuit and output the second streamed data in a different format. The controller may be configured to control operation of the write data mover circuit.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: November 12, 2019
    Assignee: XILINX, INC.
    Inventor: Sundararajarao Mohan
  • Publication number: 20190096813
    Abstract: An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Applicant: Xilinx, Inc.
    Inventors: Austin H. Lesea, Sundararajarao Mohan, Stephen M. Trimberger
  • Publication number: 20180232254
    Abstract: Embodiments herein describe techniques for executing VMs on hosts that include an accelerator. The hosts can use the accelerators to perform specialized tasks such as floating-point arithmetic, encryption, image processing, etc. Moreover, VMs can be migrated between hosts. To do so, the state of the processor is saved on the current host thereby saving the state of the VM. For example, by saving the processor state, once the data corresponding to the VM is loaded into a destination host, the processor can be initialized to the saved state in order to resume the VM. In addition to saving the processor state, the embodiments herein save the state of the accelerator on a FPGA. That is, unlike previous systems where tasks executed by the accelerator are discarded when migrating the VM, the state of the accelerator can be saved and used to initialize an FPGA accelerator in the destination host.
    Type: Application
    Filed: February 10, 2017
    Publication date: August 16, 2018
    Applicant: Xilinx, Inc.
    Inventor: Sundararajarao Mohan
  • Patent number: 9880966
    Abstract: Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: January 30, 2018
    Assignee: XILINX, INC.
    Inventors: L. James Hwang, Vinod K. Kathail, Sundararajarao Mohan, Jorge E. Carrillo, Hua Sun
  • Patent number: 9805152
    Abstract: In an example implementation, a method is provided for compiling an HLL source file including function calls to one or more hardware accelerated functions. Function calls in the HLL source file to hardware accelerated functions are identified and grouped into a plurality of subsets for exclusive implementation in programmable logic resources. Sets of configuration data are generated for configuration of the programmable logic resources to implement hardware accelerated functions for the respective subsets of function calls. An interface manager is generated and the identified function calls are replaced with interface code configured to communicate with the interface manager. The interface manager manages configuration of the programmable logic resources to switch between the sets of configuration data to implement hardware accelerated functions for different ones of the subsets.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: October 31, 2017
    Assignee: XILINX, INC.
    Inventors: Jorge E. Carrillo, Vinod K. Kathail, L. James Hwang, Sundararajarao Mohan, Hua Sun
  • Patent number: 9652570
    Abstract: Implementing a system-on-chip (SOC) design specified as a high level programming language (HLL) application may include querying, using a computer, a platform description to determine an available interface of a platform for a target integrated circuit and generating, using the computer, hardware for a function of the HLL application marked for hardware acceleration and hardware coupling the marked function with the available interface of the platform. Implementing the SOC design may also include modifying, using the computer, the HLL application with program code configured to access the generated hardware for the marked function and building, using the computer, the hardware and the software of the SOC design.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: May 16, 2017
    Assignee: XILINX, INC.
    Inventors: Vinod K. Kathail, L. James Hwang, Sundararajarao Mohan, Jorge E. Carrillo, Hua Sun, Tom Shui, Yogesh L. Chobe
  • Patent number: 9557795
    Abstract: A multi-processor system with dynamic power optimization for an integrated circuit and methods thereof are described. An input rate control signal is generated responsive to at least one input data stream. An output rate control signal is generated responsive to an output of the plurality of processors. The input rate control signal and the output rate control signal are monitored. The at least one input data stream is partitioned in response to the input rate control signal. The partitioned data is distributed to at least a portion of the plurality of processors. The plurality of processors is operated in a plurality of modes responsive to the monitoring.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: January 31, 2017
    Assignee: XILINX, INC.
    Inventors: Sabih Sabih, Sundararajarao Mohan
  • Patent number: 9444497
    Abstract: A method and apparatus for adaptively tuning an integrated circuit are disclosed. For example, an integrated circuit (IC) comprises a monitored path comprising circuit elements operating on a clock signal, where a last circuit element of the circuit elements comprises a first flip flop. The IC also comprises a second flip flop operating on an early clock signal, where the early clock signal is phase shifted from the clock signal, and where the second flip flop is coupled to the monitored path prior to the last circuit element. The IC also comprises a transition detection module for detecting when an output from the first flip flop toggles, and an error prediction module to detect a potential error on the monitored path. The IC comprises a controller that is configured to scale a voltage or a frequency of the IC.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: September 13, 2016
    Assignee: XILINX, INC.
    Inventors: Sundararajarao Mohan, Tim Tuan
  • Patent number: 9223921
    Abstract: In an example implementation, a method is provided for compiling an HLL source file. The HLL source file checked for function calls to a set of hardware-accelerated functions having hardware implementations specified in a hardware library. For each HLL function call to a hardware-accelerated function, a circuit design is retrieved from the hardware library. The circuit design specifies a hardware implementation of the hardware-accelerated function. HLL interface code configured to communicate with the hardware implementation of the hardware-accelerated function is also generated. The HLL function call to the hardware-accelerated function in the HLL source file is replaced with the generated interface code. The HLL source file is compiled to generate a program executable on a processor of a programmable IC. Configuration data is generated that implements the retrieved circuit designs on the programmable circuitry of the programmable IC.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: December 29, 2015
    Assignee: XILINX, INC.
    Inventors: Jorge E. Carrillo, L. James Hwang, Hua Sun, Sundararajarao Mohan, Vinod K. Kathail
  • Patent number: 9147024
    Abstract: Hardware and software co-synthesis performance estimation includes, for a design specified in a high level programming language and having a processor executable partition and a partition selected for hardware acceleration, estimating hardware latency for a hardware accelerator implementation of the selected partition, scheduling the selected partition using the hardware latency generating hardware partition latency information, and compiling an instrumented version of the design using a processor. The instrumented and compiled version of the design is executed generating software latency information. A design performance for the design is determined through combining the hardware partition latency information with the software latency information.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: September 29, 2015
    Assignee: XILINX, INC.
    Inventors: Vinod K. Kathail, Hua Sun, Sundararajarao Mohan, L. James Hwang, Yogesh L. Chobe
  • Patent number: 8775986
    Abstract: A method is provided for synthesizing an HLL program. For one or more variables to observe and/or control in a function of the HLL program, a first code segment is added to the function in the HLL program. For each of the one or more variables a respective second code segment is also added to the HLL program. In response to encountering the first code segment during synthesis of the HLL program, a memory is instantiated in a synthesized design. In response to encountering the second code segment during synthesis of the HLL program, a respective interface circuit is instantiated in the synthesized design. Each interface circuit is configured to replicate a state of the corresponding variable in the memory during operation of the synthesized design. A table is generated that maps names of the one or more variables to respective memory addresses in the memory.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: July 8, 2014
    Assignee: Xilinx, Inc.
    Inventors: Sundararajarao Mohan, L. James Hwang
  • Patent number: 8762916
    Abstract: A method of automatically developing a data transfer network includes determining, using a processor, a plurality of data transfers of a function of a circuit design marked for hardware acceleration within a target integrated circuit. The circuit design is specified in a high level programming language, and at least one other function of the circuit design remains executable by a microprocessor of the target integrated circuit. Each of the plurality of data transfers is characterized. Each of the plurality of data transfers is correlated with resources of the target integrated circuit. A programmatic description of a data transfer network is generated for the circuit design. The data transfer network connects the hardware accelerator and the microprocessor according to the characterizing and the correlating.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: June 24, 2014
    Assignee: Xilinx, Inc.
    Inventors: Vinod K. Kathail, L. James Hwang, Sundararajarao Mohan, Hua Sun
  • Patent number: 8327200
    Abstract: An integrated circuit (“IC”) in which a debug signal is fed back within a core block is disclosed. The core block generates the debug signal. The core block includes a hardened routing that routes the debug signal within the core block. The IC also includes a programmable routing, coupled to the core block, to route the debug signal external to the core block. The hardened routing transmits the debug signal at a faster rate than the programmable routing. Further, the IC includes a selection device, coupled to the hardened routing and the programmable routing, to select one of: the hardened routed signal or the externally routed signal. In addition, the IC includes an external debug circuit, coupled to the programmable routing, to condition the externally routed signal.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: December 4, 2012
    Assignee: Xilinx, Inc.
    Inventor: Sundararajarao Mohan
  • Patent number: 7721090
    Abstract: A method of creating a secure intellectual property (IP) representation of a circuit design for use with a software-based simulator can include translating a hardware description language representation of the circuit design into an encrypted intermediate form and compiling the intermediate form of the circuit design to produce encrypted object code. The method further can include linking the encrypted object code with a simulation kernel library thereby creating the secure IP representation of the circuit design. The secure IP can include an encrypted simulation model of the circuit design and a simulation kernel configured to execute the encrypted simulation model.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: May 18, 2010
    Assignee: Xilinx, Inc.
    Inventors: Kumar Deepak, Satish R. Ganesan, Jimmy Zhenming Wang, Sundararajarao Mohan, Ralph D. Wittig, Hem C. Neema
  • Patent number: 7676661
    Abstract: A fast linked multiprocessor network including a plurality of processing modules implemented on a field programmable gate array and a plurality of configurable uni-directional links coupled among at least two of the plurality processing modules provide a streaming communication channel between at least two of the plurality of processing modules. Such configuration provides a function accelerator that can feed at least one processor with data values using one custom instruction to put data values on at least one uni-directional serial link and that can extract data values from at least one processor using one custom instruction to get data values from the at least one uni-directional serial link.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: March 9, 2010
    Assignee: Xilinx, Inc.
    Inventors: Sundararajarao Mohan, Satish R. Ganesan, Goran Bilski
  • Patent number: 7310594
    Abstract: A multiprocessor system (10) includes a plurality of processing engines (14, 16, 18, 20, 22, 32, 33 and 35) including a software processing engine and a hardware processing engine implemented on a single silicon device defined by a single programming language and the single programming language tagged with at least one macro. The multiprocessor system further includes connectivity (37 and 40) between the plurality of processing engines defined by the single programming language and by the single programming language tagged with at least one macro.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: December 18, 2007
    Assignee: Xilinx, Inc.
    Inventors: Satish R. Ganesan, Usha Prabhu, Sundararajarao Mohan, Ralph D. Wittig, David W. Bennett
  • Patent number: 7248073
    Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: July 24, 2007
    Assignee: Xilinx, Inc.
    Inventors: Bernard J. New, Ralph D. Wittig, Sundararajarao Mohan
  • Patent number: 7243330
    Abstract: Method and apparatus for providing self-implementing hardware-software libraries is described. One aspect of the invention relates to designing an embedded system for an integrated circuit. A hardware platform is defined. A software platform is defined having a plurality of software components, including a library. Hardware component dependency data associated with the library is identified. At least one hardware component is added to the hardware platform in response to the hardware component dependency data.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: July 10, 2007
    Assignee: Xilinx, Inc.
    Inventors: Satish R. Ganesan, Amit Kasat, Sathyanarayanan Thammanur, Sundararajarao Mohan, Usha Prabhu, Ralph D. Wittig