Abstract: In an example implementation, a method is provided for compiling an HLL source file. The HLL source file checked for function calls to a set of hardware-accelerated functions having hardware implementations specified in a hardware library. For each HLL function call to a hardware-accelerated function, a circuit design is retrieved from the hardware library. The circuit design specifies a hardware implementation of the hardware-accelerated function. HLL interface code configured to communicate with the hardware implementation of the hardware-accelerated function is also generated. The HLL function call to the hardware-accelerated function in the HLL source file is replaced with the generated interface code. The HLL source file is compiled to generate a program executable on a processor of a programmable IC. Configuration data is generated that implements the retrieved circuit designs on the programmable circuitry of the programmable IC.

Abstract: Hardware and software co-synthesis performance estimation includes, for a design specified in a high level programming language and having a processor executable partition and a partition selected for hardware acceleration, estimating hardware latency for a hardware accelerator implementation of the selected partition, scheduling the selected partition using the hardware latency generating hardware partition latency information, and compiling an instrumented version of the design using a processor. The instrumented and compiled version of the design is executed generating software latency information. A design performance for the design is determined through combining the hardware partition latency information with the software latency information.

Abstract: A method is provided for synthesizing an HLL program. For one or more variables to observe and/or control in a function of the HLL program, a first code segment is added to the function in the HLL program. For each of the one or more variables a respective second code segment is also added to the HLL program. In response to encountering the first code segment during synthesis of the HLL program, a memory is instantiated in a synthesized design. In response to encountering the second code segment during synthesis of the HLL program, a respective interface circuit is instantiated in the synthesized design. Each interface circuit is configured to replicate a state of the corresponding variable in the memory during operation of the synthesized design. A table is generated that maps names of the one or more variables to respective memory addresses in the memory.

Abstract: A method of automatically developing a data transfer network includes determining, using a processor, a plurality of data transfers of a function of a circuit design marked for hardware acceleration within a target integrated circuit. The circuit design is specified in a high level programming language, and at least one other function of the circuit design remains executable by a microprocessor of the target integrated circuit. Each of the plurality of data transfers is characterized. Each of the plurality of data transfers is correlated with resources of the target integrated circuit. A programmatic description of a data transfer network is generated for the circuit design. The data transfer network connects the hardware accelerator and the microprocessor according to the characterizing and the correlating.

Abstract: An integrated circuit (“IC”) in which a debug signal is fed back within a core block is disclosed. The core block generates the debug signal. The core block includes a hardened routing that routes the debug signal within the core block. The IC also includes a programmable routing, coupled to the core block, to route the debug signal external to the core block. The hardened routing transmits the debug signal at a faster rate than the programmable routing. Further, the IC includes a selection device, coupled to the hardened routing and the programmable routing, to select one of: the hardened routed signal or the externally routed signal. In addition, the IC includes an external debug circuit, coupled to the programmable routing, to condition the externally routed signal.

Abstract: A method of creating a secure intellectual property (IP) representation of a circuit design for use with a software-based simulator can include translating a hardware description language representation of the circuit design into an encrypted intermediate form and compiling the intermediate form of the circuit design to produce encrypted object code. The method further can include linking the encrypted object code with a simulation kernel library thereby creating the secure IP representation of the circuit design. The secure IP can include an encrypted simulation model of the circuit design and a simulation kernel configured to execute the encrypted simulation model.

Abstract: A fast linked multiprocessor network including a plurality of processing modules implemented on a field programmable gate array and a plurality of configurable uni-directional links coupled among at least two of the plurality processing modules provide a streaming communication channel between at least two of the plurality of processing modules. Such configuration provides a function accelerator that can feed at least one processor with data values using one custom instruction to put data values on at least one uni-directional serial link and that can extract data values from at least one processor using one custom instruction to get data values from the at least one uni-directional serial link.

Abstract: A multiprocessor system (10) includes a plurality of processing engines (14, 16, 18, 20, 22, 32, 33 and 35) including a software processing engine and a hardware processing engine implemented on a single silicon device defined by a single programming language and the single programming language tagged with at least one macro. The multiprocessor system further includes connectivity (37 and 40) between the plurality of processing engines defined by the single programming language and by the single programming language tagged with at least one macro.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: Method and apparatus for providing self-implementing hardware-software libraries is described. One aspect of the invention relates to designing an embedded system for an integrated circuit. A hardware platform is defined. A software platform is defined having a plurality of software components, including a library. Hardware component dependency data associated with the library is identified. At least one hardware component is added to the hardware platform in response to the hardware component dependency data.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: A softPAL implementation and mapping method are described. The implementation utilizes both LUTs and architecture-specific logic circuits to implement softPAL functions, and selects from several implementations in order to decrease delay in function implementation. The method describes techniques for estimating p-terms in a 2-bounded sub-graph, factoring methods, mapping strategies for LUTs and dedicated logic elements, and delay optimization of critical paths.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: An apparatus for implementing fast sum-of-products logic in an FPGA is disclosed. The apparatus includes a CLB including a plurality of slices and a second-level logic circuit to combine the outputs of the slices. Typically, the second-level logic circuit is an OR gate or its equivalent that implements the sum portion of the sum-of-products expression. Alternatively, a combining gate may be included within the slice to combine the output of one slice with the output of another slice. In this case the combing gates of each of the slices are connected in series to sum the result of the product operation of a given slice with the product operations from preceding slices. The slice may also include a dedicated function generator to increase the performance of each slice to implement wide functions, particularly sum-of-products functions. The dedicated function generator may include an AND gate and an OR gate with a multiplexer as a selector.

Abstract: An FPGA is described using optical waveguides for routing signals through the FPGA. The routing is controlled electrically. Either coupling waveguides or resonant disks can be used for routing the optical signals. Lookup tables convert optical input signals to electrical signals for selecting values in the lookup table.

Abstract: A method for implementing a large multiplexer with FPGA lookup tables. Logic that defines a multiplexer is detected and implemented according to the number of inputs and the target FPGA architecture. In one situation, a large multiplexer is implemented in two stages. The first stage implements wide AND functions of each of the input signals using lookup tables and carry logic. In a second stage, the resulting decoded input signals are combined in a wide OR gate again formed from lookup tables and a carry chain. In another situation, the multiplexer is implemented as a tree structure using lookup tables that implement 2:1 multiplexers in combination with other 2:1 multiplexers provided by configurable logic blocks of the FPGA.