Abstract: An approach is provided in which a computing system captures content included in a history buffer entry that corresponds to a flush ITAG. The computing system, in turn, uses an execution unit to transmit the content over a results bus to multiple registers and restore at least one of the registers accordingly.

Abstract: An approach is provided in which a computing system captures content included in a history buffer entry that corresponds to a flush ITAG. The computing system, in turn, uses an execution unit to transmit the content over a results bus to multiple registers and restore at least one of the registers accordingly.

Abstract: Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level mechanism to overcome a system hang. Such a multi-slice processor includes a plurality of execution slices and a dispatch network of the multi-slice processor implementing a hardware level mechanism to overcome a system hang. Operation of such a multi-slice processor includes, storing, in one or more logical units of a plurality of logical units of an age array, a logical value representing a relative age between instructions; propagating, in response to a current instruction being in a hang state, a hang signal to the plurality of logical units of the age array; in response to the hang signal, generating, from the plurality of logical units, a plurality of logical output values indicating a next instruction ready for execution; and issuing the next instruction for execution.

Abstract: Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.

Abstract: Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.

Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices coupled via a results bus includes: retrieving, from the results bus into an entry of a register file of an execution slice, speculative result data of a load instruction generated by a load/store slice; and determining, from the load/store slice after expiration of a predetermined period of time, whether the result data is valid.

Abstract: Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus, including: for a target instruction targeting a logical register, determining whether an entry in a general purpose register representing the logical register is pending a flush; if the entry in the general purpose register representing the logical register is pending a flush: cancelling the flush in the entry of the general purpose register; storing the target instruction in the entry of the general purpose register representing the logical register, and if an entry in a history buffer targeting the logical register is pending a restore, cancelling the restore for the entry of the history buffer.

Abstract: Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus includes: receiving, by an execution slice, a producer instruction, including: storing, in an entry of an issue queue, the producer instruction; and storing, in a register, an issue queue entry identifier representing the entry of the issue queue in which the producer instruction is stored; receiving, by the execution slice, a source instruction, the source instruction dependent upon the result of the producer instruction, including: storing, in another entry of the issue queue, the source instruction and the issue queue entry identifier of the producer instruction; determining in dependence upon the issue queue entry identifier of the producer instruction that the producer instruction has issued from the issue queue; and responsive to the determination that the producer instruction has issued from the issue queue, issuing the source instruction from the issue queue.

Abstract: Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus includes: receiving, by an execution slice, a producer instruction, including: storing, in an entry of an issue queue, the producer instruction; and storing, in a register, an issue queue entry identifier representing the entry of the issue queue in which the producer instruction is stored; receiving, by the execution slice, a source instruction, the source instruction dependent upon the result of the producer instruction, including: storing, in another entry of the issue queue, the source instruction and the issue queue entry identifier of the producer instruction; determining in dependence upon the issue queue entry identifier of the producer instruction that the producer instruction has issued from the issue queue; and responsive to the determination that the producer instruction has issued from the issue queue, issuing the source instruction from the issue queue.

Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices coupled via a results bus includes: retrieving, from the results bus into an entry of a register file of an execution slice, speculative result data of a load instruction generated by a load/store slice; and determining, from the load/store slice after expiration of a predetermined period of time, whether the result data is valid.

Abstract: Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus, including: for a target instruction targeting a logical register, determining whether an entry in a general purpose register representing the logical register is pending a flush; if the entry in the general purpose register representing the logical register is pending a flush: cancelling the flush in the entry of the general purpose register; storing the target instruction in the entry of the general purpose register representing the logical register, and if an entry in a history buffer targeting the logical register is pending a restore, cancelling the restore for the entry of the history buffer.

Abstract: In an approach for decreasing a rate of logic voltage level transitions in a multiplexor, one of a plurality of inputs to a multiplexor is selected with a first multiplexor select value at a first clock, wherein each input to the multiplexor is identified as one of i) valid and ii) invalid and the first multiplexor select value is latched in a latch until the first multiplexor select value is replaced by a second multiplexor select value. The second multiplexor select value is determined. The second multiplexor select value is applied to the multiplexor at a second clock if and only if the second multiplexor select value is different from the first multiplexor select value and the second multiplexor select value selects a valid input, wherein the second clock follows the first clock. Subsequent to applying the second multiplexor select value, the second multiplexor value is latched in the latch.

Abstract: In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A major signal is generated that identifies an oldest ready instruction in the first age array and a subset signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.

Abstract: Techniques disclosed herein describe a variable latency pipe for interleaving instruction tags in a processor. According to one embodiment presented herein, an instruction tag is associated with an instruction upon issue of the instruction from the issue queue. One of a plurality of positions in the latency pipe is determined. The pipe stores one or more instruction tags, each associated with a respective instruction. The pipe also stores the instruction tags in a respective position based on the latency of each respective instruction. The instruction tag is stored at the determined position in the pipe.

Abstract: Techniques disclosed herein describe a variable latency pipe for interleaving instruction tags in a processor. According to one embodiment presented herein, an instruction tag is associated with an instruction upon issue of the instruction from the issue queue. One of a plurality of positions in the latency pipe is determined. The pipe stores one or more instruction tags, each associated with a respective instruction. The pipe also stores the instruction tags in a respective position based on the latency of each respective instruction. The instruction tag is stored at the determined position in the pipe.

Abstract: Techniques are disclosed for back-to-back issue of instructions in a processor. A first instruction is stored in a queue position in an issue queue. The issue queue stores instructions in a corresponding queue position. The first instruction includes a target instruction tag and at least a source instruction tag. The target instruction tag is stored in a table storing a plurality of target instruction tags associated with a corresponding instruction. Each stored target instruction tag specifies a logical register that stores a target operand. Upon determining, based on the source instruction tag associated with the first instruction and the target instruction tag associated with a second instruction, that the first instruction is dependent on the second instruction, a pointer to the first instruction is associated with the second instruction. The pointer is used to wake up the first instruction upon issue of the second instruction.

Abstract: Techniques are disclosed for back-to-back issue of instructions in a processor. A first instruction is stored in a queue position in an issue queue. The issue queue stores instructions in a corresponding queue position. The first instruction includes a target instruction tag and at least a source instruction tag. The target instruction tag is stored in a table storing a plurality of target instruction tags associated with a corresponding instruction. Each stored target instruction tag specifies a logical register that stores a target operand. Upon determining, based on the source instruction tag associated with the first instruction and the target instruction tag associated with a second instruction, that the first instruction is dependent on the second instruction, a pointer to the first instruction is associated with the second instruction. The pointer is used to wake up the first instruction upon issue of the second instruction.

Abstract: Techniques are disclosed for issuing instructions in a processor. According to one embodiment of the present disclosure, an instruction tag is broadcast to wake up a plurality of instructions stored in an issue queue that are dependent on an issued instruction associated with the instruction tag. Each of the plurality of instructions has an execution latency. One or more of the instructions having an execution that will collide with an execution of one of the issued instructions if issued in a next clock cycle are identified based on the execution latencies. The identified one or more instructions are delayed from issue by at least one clock cycle after the next clock cycle.