Patents by Inventor Sundeep Chadha
Sundeep Chadha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8745307Abstract: An approach identifies an amount of high order bits used to store a memory address in a memory address field that is included in a memory. This approach calculates at least one minimum number of low order bits not used to store the address with the calculation being based on the identified amount of high order bits. The approach retrieves a data element from one of the identified minimum number of low order bits of the address field and also retrieves a second data element from one of the one of the identified minimum number of low order bits of the address field.Type: GrantFiled: May 13, 2010Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Cathy May, Naresh Nayar, Randal Craig Swanberg
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Publication number: 20140143523Abstract: In a processor core, high latency operations are tracked in entries of a data structure associated with an execution unit of the processor core. In the execution unit, execution of an instruction dependent on a high latency operation tracked by an entry of the data structure is speculatively finished prior to completion of the high latency operation. Speculatively finishing the instruction includes reporting an identifier of the entry to completion logic of the processor core and removing the instruction from an execution pipeline of the execution unit. The completion logic records dependence of the instruction on the high latency operation and commits execution results of the instruction to an architected state of the processor only after successful completion of the high latency operation.Type: ApplicationFiled: November 16, 2012Publication date: May 22, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: SUNDEEP CHADHA, BRYAN LLOYD, DUNG Q. NGUYEN, DAVID S. RAY, BENJAMIN W. STOLT
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Publication number: 20140122840Abstract: A processor includes an execution unit, a first level register file, a second level register file, a plurality of storage locations and a register file bypass controller. The first and second level register files are comprised of physical registers, with the first level register file more efficiently accessed relative to the second level register file. The register file bypass controller is coupled with the execution unit and second level register file. The register file bypass controller determines whether an instruction indicates a logical register is unmapped from a physical register in the first level register file. The register file controller also loads data into one of the storage locations and selects one of the storage locations as input to the execution unit, without mapping the logical register to one of the physical registers in the first level register file.Type: ApplicationFiled: October 31, 2012Publication date: May 1, 2014Inventors: Christopher M. Abernathy, Mary D. Brown, Sundeep Chadha, Dung Q. Nguyen
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Publication number: 20110283040Abstract: An approach identifies an amount of high order bits used to store a memory address in a memory address field that is included in a memory. This approach calculates at least one minimum number of low order bits not used to store the address with the calculation being based on the identified amount of high order bits. The approach retrieves a data element from one of the identified minimum number of low order bits of the address field and also retrieves a second data element from one of the one of the identified minimum number of low order bits of the address field.Type: ApplicationFiled: May 13, 2010Publication date: November 17, 2011Applicant: International Business Machines CorporationInventors: Sundeep Chadha, Cathy May, Naresh Nayar, Randal Craig Swanberg
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Publication number: 20110276778Abstract: An apparatus, system, and method are disclosed for improved support of MPS segments in a microprocessor. The virtual address is used to generate possible TLB index values for each of the supported page sizes of the MPS segment associated with the virtual address. The possible TLB index values may be a hash generated using the virtual address and one of the supported page sizes. The TLB is searched for actual TLB index values that match the possible TLB index values calculated using the different supported page sizes. TLB entries associated with those actual TLB index values are checked to determine whether any TLB entry is associated with the virtual address. If no match is found, the real address is retrieved from the PT. The actual page size in the PT is used to generate an actual TLB index value for the virtual address and the TLB entry is inserted into the TLB.Type: ApplicationFiled: May 7, 2010Publication date: November 10, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Miles R. Dooley, Sundeep Chadha, Naresh Nayar, Randal C. Swanberg
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Patent number: 7882278Abstract: A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.Type: GrantFiled: January 30, 2009Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Mark Anthony Check, Bernard Charles Drerup, Michael Grassi
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Patent number: 7853420Abstract: An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.Type: GrantFiled: April 14, 2008Date of Patent: December 14, 2010Assignee: International Business Machines CorporationInventors: Parag Birmiwal, Sundeep Chadha, Tilman Gloekler, Johannes Koesters
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Patent number: 7761825Abstract: An apparatus, computer system, and storage medium that, in an embodiment, receive elements and a goal for each of the elements. In various embodiments, the elements may represent commands or parameter values for a device to be tested. Testcases are generated based on the elements. If the numbers of testcases for the elements are equally distant from their goals, then a new testcase is generated based on an element chosen at random. But, if the numbers of testcases are not equally distant from their goals, then the new testcase is generated based on the element whose number of testcases if furthest from its respective goal. The number of testcases associated with the chosen element is then incremented, and the process is repeated. In this way, the generated testcases are based on the numbers of previously generated testcases, which, in an embodiment, results in more complete coverage of testcases for the device under test.Type: GrantFiled: July 24, 2008Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventor: Sundeep Chadha
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Publication number: 20090138629Abstract: A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.Type: ApplicationFiled: January 30, 2009Publication date: May 28, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sundeep Chadha, Mark Anthony Check, Bernard Charles Drerup, Michael Grassi
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Patent number: 7516430Abstract: A method, apparatus, system, and signal-bearing medium that, in an embodiment, receive elements and a goal for each of the elements. In various embodiments, the elements may represent commands or parameter values for a device to be tested. Testcases are generated based on the elements. If the numbers of testcases for the elements are equally distant from their goals, then a new testcase is generated based on an element chosen at random. But, if the numbers of testcases are not equally distant from their goals, then the new testcase is generated based on the element whose number of testcases if furthest from its respective goal. The number of testcases associated with the chosen element is then incremented, and the process is repeated. In this way, the generated testcases are based on the numbers of previously generated testcases, which, in an embodiment, results in more complete coverage of testcases for the device under test.Type: GrantFiled: December 23, 2004Date of Patent: April 7, 2009Assignee: International Business Machines CorporationInventor: Sundeep Chadha
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Patent number: 7505405Abstract: A method, apparatus and computer program product are provided for optimizing packet flow control through buffer status forwarding. A sending device includes buffer status information of the sending device in transactions being sent to a receiving device. The receiving device uses the buffer status information of the sending device for selecting transactions to offload.Type: GrantFiled: October 8, 2004Date of Patent: March 17, 2009Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Bernard Charles Drerup
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Patent number: 7502966Abstract: A current parameter file is periodically selected at random from an active pool, and testcases are generated and executed from the current parameter file against a device, where the execution of the testcases against the device hits events generated by the device over periods. A determination is made whether a number of the events hit by all testcases from the current parameter file in a current period meets a goal for the current parameter file. If the determination is false, the current parameter file is added to a miss pool if a number events for all periods for the current parameter file does not meet a goal for all periods for the current parameter file; the current parameter file is added to a retired pool if the number of events for all periods for the current parameter file meets the goal for all periods for the current parameter file; and the current parameter file is changed to another parameter file from the active pool.Type: GrantFiled: February 9, 2006Date of Patent: March 10, 2009Assignee: International Business Machines CorporationInventors: Olga Buchonina, Sundeep Chadha, Maureen Terese Davis, Anh Tran Vinh, Trac Minh Vu
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Patent number: 7493426Abstract: A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.Type: GrantFiled: January 31, 2005Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Mark Anthony Check, Bernard Charles Drerup, Michael Grassi
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Patent number: 7464354Abstract: An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.Type: GrantFiled: December 8, 2005Date of Patent: December 9, 2008Assignee: International Business Machines CorporationInventors: Parag Birmiwal, Sundeep Chadha, Tilman Gloekler, Johannes Koesters
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Publication number: 20080288903Abstract: An apparatus, computer system, and storage medium that, in an embodiment, receive elements and a goal for each of the elements. In various embodiments, the elements may represent commands or parameter values for a device to be tested. Testcases are generated based on the elements. If the numbers of testcases for the elements are equally distant from their goals, then a new testcase is generated based on an element chosen at random. But, if the numbers of testcases are not equally distant from their goals, then the new testcase is generated based on the element whose number of testcases if furthest from its respective goal. The number of testcases associated with the chosen element is then incremented, and the process is repeated. In this way, the generated testcases are based on the numbers of previously generated testcases, which, in an embodiment, results in more complete coverage of testcases for the device under test.Type: ApplicationFiled: July 24, 2008Publication date: November 20, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Sundeep Chadha
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Publication number: 20080195339Abstract: An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.Type: ApplicationFiled: April 14, 2008Publication date: August 14, 2008Inventors: Parag Birmiwal, Sundeep Chadha, Tilman Gloekler, Johannes Koesters
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Publication number: 20080195340Abstract: An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.Type: ApplicationFiled: April 14, 2008Publication date: August 14, 2008Inventors: Parag Birmiwal, Sundeep Chadha, Tilman Gloekler, Johannes Koesters
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Publication number: 20070220339Abstract: A current parameter file is periodically selected at random from an active pool, and testcases are generated and executed from the current parameter file against a device, where the execution of the testcases against the device hits events generated by the device over periods. A determination is made whether a number of the events hit by all testcases from the current parameter file in a current period meets a goal for the current parameter file. If the determination is false, the current parameter file is added to a miss pool if a number events for all periods for the current parameter file does not meet a goal for all periods for the current parameter file; the current parameter file is added to a retired pool if the number of events for all periods for the current parameter file meets the goal for all periods for the current parameter file; and the current parameter file is changed to another parameter file from the active pool.Type: ApplicationFiled: February 9, 2006Publication date: September 20, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Olga Buchonina, Sundeep Chadha, Maureen Davis, Anh Vinh, Trac Vu
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Publication number: 20070220390Abstract: A method for verifying the equivalence of two representations of a stimulus pattern for testing a design is disclosed. The method includes receiving a base pattern file representing the stimulus pattern in a first file format. A derivative pattern file in a second file format is generated from the base pattern file. The derivative pattern file is parsed to create a first testing file in a third file format, and the first testing file is simulated against the design in a first simulation. Whether the first testing file passed the first simulation against the design is determined, and in response to determining that the first testing file does not pass the first simulation against the design, the base pattern file is parsed to create a second testing file in the third file format. The second testing file is simulated in a second simulation.Type: ApplicationFiled: March 4, 2006Publication date: September 20, 2007Inventors: Sarah Bird, Sundeep Chadha, Maureen Davis, Kirk Morrow, Tung Pham
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Publication number: 20070168741Abstract: A computer-implemented processing tool is provided for facilitating debugging of simulation results obtained for an optimized simulation model of a device having hierarchically-connected components. The tool includes: receiving a component port name of the device to be searched; automatically checking a hardware descriptive language description of the device for a next higher level component of the device that instantiates the component having the component port name to be searched; locating a signal name in the next higher level component that is connected to the port identified by the component port name; and outputting the signal name as a signal that drives the named component port when the signal is other than a port signal of the next higher level component. Otherwise, repeating the automatically checking and the locating when the signal name in the next higher level component is a port signal of a further higher level component.Type: ApplicationFiled: November 17, 2005Publication date: July 19, 2007Applicant: International Business Machines CorporationInventors: Sundeep Chadha, Sudhi Proch