Patents by Inventor Sunfei Fang
Sunfei Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070194387Abstract: A semiconductor device comprises a gate electrode stack having sidewalls and a top surface with a gate dielectric layer and the gate electrode, and LDD/LDS regions in the substrate aligned with the stack. Conformal L-shaped etch-stop layers with a thickness from about 50 ? to about 200 ? are formed with a vertical leg on the sidewalls of the stack and a horizontal leg reaching over the LDD/LDS regions next to the stack. RSD regions are formed in contact with the substrate aside from the etch-stop layers. The RSD regions cover the horizontal leg of the etch-stop layer and cover at least a portion of the vertical leg of the etch-stop layer on the sidewall of the gate electrode.Type: ApplicationFiled: February 21, 2006Publication date: August 23, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas Dyer, Sunfei Fang
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Patent number: 7223691Abstract: A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.Type: GrantFiled: October 14, 2004Date of Patent: May 29, 2007Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Lawrence A. Clevenger, Timothy J. Dalton, Patrick W. DeHaven, Chester T. Dziobkowski, Sunfei Fang, Terry A. Spooner, Tsong-Lin L. Tai, Kwong Hon Wong, Chin-Chao Yang
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Patent number: 7220662Abstract: Fully silicided planar field effect transistors are formed by avoiding the conventional chemical-mechanical polishing step to expose the silicon gate by etching the sidewalls down to the silicon; depositing a sacrificial oxide layer thinner on the top of gate and sidewall of spacers, but thicker over the S/D areas, etching the oxide to expose the top of stacked gate while protecting the S/D; recessing the silicon; stripping the oxide; depositing metal and annealing to form silicide over the gate and S/D.Type: GrantFiled: January 10, 2005Date of Patent: May 22, 2007Assignee: International Business Machines CorporationInventors: Huilong Zhu, Sunfei Fang, Zhijiong Luo
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Publication number: 20070105299Abstract: A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.Type: ApplicationFiled: November 10, 2005Publication date: May 10, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sunfei Fang, Jun Kim, Zhijiong Luo, Hung Ng, Nivo Rovedo, Young Teh
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Publication number: 20070034967Abstract: A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to a semiconductor metal alloy in a second MOSFET type region. In one embodiment, the gate stack in a first MOSFET region is recessed prior to forming the metal-containing layer so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer is thinned over one MOSFET region relative to the other MOSFET region prior to the conversion process.Type: ApplicationFiled: October 2, 2006Publication date: February 15, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hasan Nayfeh, Mahender Kumar, Sunfei Fang, Jakub Kedzierski, Cyril Cabral
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Patent number: 7151023Abstract: A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to a semiconductor metal alloy in a second MOSFET type region. In one embodiment, the gate stack in a first MOSFET region is recessed prior to forming the metal-containing layer so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer is thinned over one MOSFET region relative to the other MOSFET region prior to the conversion process.Type: GrantFiled: August 1, 2005Date of Patent: December 19, 2006Assignee: International Business Machines CorporationInventors: Hasan M. Nayfeh, Mahender Kumar, Sunfei Fang, Jakub T Kedzierski, Cyril Cabral, Jr.
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Publication number: 20060244075Abstract: A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and second S/D regions, respective. First and second silicide regions are formed such that the first silicide region is in direct physical contact with the first S/D region and the first S/D extension region, whereas the second silicide region is in direct physical contact with the second S/D region and the second S/D extension region. The first silicide region is thinner for regions in contact with first S/D extension region than for regions in contact with the first S/D region. Similarly, the second silicide region is thinner for regions in contact with second S/D extension region than for regions in contact with the second S/D region.Type: ApplicationFiled: April 27, 2005Publication date: November 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiangdong Chen, Sunfei Fang, Zhijiong Luo, Haining Yang, Huilong Zhu
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Patent number: 7122472Abstract: A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device having a first well region in a semiconductor substrate, first source/drain silicide areas in the first well region, and a first type gate isolated from the first source/drain silicide areas; forming a second type semiconductor device having a second well region in the semiconductor substrate, second source/drain silicide areas in the second well region, and a second type gate isolated from the second source/drain silicide areas; selectively forming a first metal layer over the second type semiconductor device; performing a first fully silicided (FUSI) gate formation on only the second type gate; depositing a second metal layer over the first and second type semiconductor devices; and performing a second FUSI gate formation on only the first type gate.Type: GrantFiled: December 2, 2004Date of Patent: October 17, 2006Assignee: International Business Machines CorporationInventors: Sunfei Fang, Cyril Cabral, Jr., Chester T. Dziobkowski, Christian Lavoie, Clement H. Wann
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Patent number: 7112481Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.Type: GrantFiled: October 20, 2005Date of Patent: September 26, 2006Assignee: International Business Machines CorporationInventors: Sunfei Fang, Cyril Cabral, Jr., Chester T. Dziobkowski, John J. Ellis-Monaghan, Christian Lavoie, Zhijiong Luo, James S. Nakos, An L. Steegen, Clement H. Wann
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Patent number: 7105440Abstract: A process for forming a metal suicide gate in an FET device, where the suicide is self-forming (that is, formed without the need for a separate metal/silicon reaction step), and no CMP or etchback of the silicon material is required. A first layer of silicon material (polysilicon or amorphous silicon) is formed overlying the gate dielectric; a layer of metal is then formed on the first layer, and a second layer of silicon on the metal layer. A high-temperature (>700° C.) processing step, such as source/drain activation anneal, is subsequently performed; this step is effective to form a silicide layer above the gate dielectric by reaction of the metal with silicon in the first layer. A second high-temperature processing step (such as source/drain silicidation) may be performed which is effective to form a second silicide layer from silicon in the second layer.Type: GrantFiled: January 13, 2005Date of Patent: September 12, 2006Assignee: International Business Machines CorporationInventors: Zhijiong Luo, Sunfei Fang, Huilong Zhu
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Publication number: 20060163569Abstract: A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.Type: ApplicationFiled: September 2, 2005Publication date: July 27, 2006Inventors: Min-chul Sun, Ja-hum Ku, Brian Greene, Manfred Eller, Wee Tan, Sunfei Fang, Zhijiong Luo
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Publication number: 20060154461Abstract: Fully silicided planar field effect transistors are formed by avoiding the conventional chemical-mechanical polishing step to expose the silicon gate by etching the sidewalls down to the silicon; depositing a sacrificial oxide layer thinner on the top of gate and sidewall of spacers, but thicker over the S/D areas, etching the oxide to expose the top of stacked gate while protecting the S/D; recessing the silicon; stripping the oxide; depositing metal and annealing to form silicide over the gate and S/D.Type: ApplicationFiled: January 10, 2005Publication date: July 13, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huilong Zhu, Sunfei Fang, Zhijiong Luo
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Publication number: 20060154413Abstract: A process for forming a metal suicide gate in an FET device, where the suicide is self-forming (that is, formed without the need for a separate metal/silicon reaction step), and no CMP or etchback of the silicon material is required. A first layer of silicon material (polysilicon or amorphous silicon) is formed overlying the gate dielectric; a layer of metal is then formed on the first layer, and a second layer of silicon on the metal layer. A high-temperature (>700° C.) processing step, such as source/drain activation anneal, is subsequently performed; this step is effective to form a silicide layer above the gate dielectric by reaction of the metal with silicon in the first layer. A second high-temperature processing step (such as source/drain silicidation) may be performed which is effective to form a second silicide layer from silicon in the second layer.Type: ApplicationFiled: January 13, 2005Publication date: July 13, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhijiong Luo, Sunfei Fang, Huilong Zhu
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Patent number: 7067368Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.Type: GrantFiled: October 20, 2005Date of Patent: June 27, 2006Assignee: International Business Machines CorporationInventors: Sunfei Fang, Cyril Cabral, Jr., Chester T. Dziobkowski, John J. Ellis-Monaghan, Christian Lavoie, Zhijiong Luo, James S. Nakos, An L. Steegen, Clement H. Wann
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Patent number: 7064025Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.Type: GrantFiled: December 2, 2004Date of Patent: June 20, 2006Assignee: International Business Machines CorporationInventors: Sunfei Fang, Cyril Cabral, Jr., Chester T. Dziobkowski, John J. Ellis-Monaghan, Christian Lavoie, Zhijiong Luo, James S. Nakos, An L. Steegen, Clement H. Wann
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Publication number: 20060121664Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.Type: ApplicationFiled: October 20, 2005Publication date: June 8, 2006Applicant: International Business Machines CorporationInventors: Sunfei Fang, Cyril Cabral, Chester Dziobkowski, John Ellis-Monaghan, Christian Lavoie, Zhijiong Luo, James Nakos, An Steegen, Clement Wann
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Publication number: 20060121665Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.Type: ApplicationFiled: October 20, 2005Publication date: June 8, 2006Applicant: International Business Machines CorporationInventors: Sunfei Fang, Cyril Cabral, Chester Dziobkowski, John Ellis-Monaghan, Christian Lavoie, Zhijiong Luo, James Nakos, An Steegen, Clement Wann
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Publication number: 20060121663Abstract: A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device having a first well region in a semiconductor substrate, first source/drain silicide areas in the first well region, and a first type gate isolated from the first source/drain silicide areas; forming a second type semiconductor device having a second well region in the semiconductor substrate, second source/drain silicide areas in the second well region, and a second type gate isolated from the second source/drain silicide areas; selectively forming a first metal layer over the second type semiconductor device; performing a first fully silicided (FUSI) gate formation on only the second type gate; depositing a second metal layer over the first and second type semiconductor devices; and performing a second FUSI gate formation on only the first type gate.Type: ApplicationFiled: December 2, 2004Publication date: June 8, 2006Applicant: International Business Machines CorporationInventors: Sunfei Fang, Cyril Cabral, Chester Dziobkowski, Christian Lavoie, Clement Wann
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Publication number: 20060121662Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.Type: ApplicationFiled: December 2, 2004Publication date: June 8, 2006Applicant: International Business Machines CorporationInventors: Sunfei Fang, Cyril Cabral, Chester Dziobkowski, John Ellis-Monaghan, Christian Lavoie, Zhijiong Luo, James Nakos, An Steegen, Clement Wann
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Publication number: 20060084256Abstract: A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.Type: ApplicationFiled: October 14, 2004Publication date: April 20, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Lawrence Clevenger, Timothy Dalton, Patrick DeHaven, Chester Dziobkowski, Sunfei Fang, Terry Spooner, Tsong-Lin Tai, Kwong Wong, Chin-Chao Yang