Patents by Inventor Sung Bum Bae
Sung Bum Bae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150194363Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.Type: ApplicationFiled: July 7, 2014Publication date: July 9, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Chi Hoon JUN, Sang Choon KO, Seok-Hwan MOON, Woojin CHANG, Sung-Bum BAE, Young Rak PARK, Je Ho NA, Jae Kyoung MUN, Eun Soo NAM
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Publication number: 20150187886Abstract: Provided is a nitride semiconductor device including: a substrate having through via holes; first and second nitride semiconductor layers sequentially stacked on the substrate; drain electrodes and source electrodes provided on the second nitride semiconductor layer; and an insulating pattern provided on the second nitride semiconductor layer, the insulating pattern having upper via holes provided on the drain electrodes, wherein the through via holes are extended into the first and second nitride semiconductor layers and expose a bottom of each of the source electrodes.Type: ApplicationFiled: June 23, 2014Publication date: July 2, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Young Rak PARK, Sang Choon KO, Woojin CHANG, Jae Kyoung MUN, Sung-Bum BAE
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Publication number: 20150187599Abstract: Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.Type: ApplicationFiled: June 20, 2014Publication date: July 2, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Sang Choon KO, Jae Kyoung MUN, Woojin CHANG, Sung-Bum BAE, Young Rak PARK, Chi Hoon JUN, Seok-Hwan MOON, Woo-Young JANG, Jeong-Jin KIM, Hyungyu JANG, Je Ho NA, Eun Soo NAM
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Publication number: 20150155434Abstract: Disclosed are a light emitting diode including: a buffer layer formed on a substrate; a Distributed Bragg Reflector (DBR) formed in a multilayer structure, in which mask patterns including opening regions and semiconductor layers formed on the mask patterns while being filled in the opening regions of the mask patterns are alternately formed, and formed on the buffer layer; and a light emitting structure formed on the DBR, and a manufacturing method thereof.Type: ApplicationFiled: February 27, 2014Publication date: June 4, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Sung Bock KIM, Sung Bum BAE
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Patent number: 9041012Abstract: A microarray-type nitride light emitting device includes a light emitting semiconductor layer; and a multilayered transparent contact layer to divide a plane of the light emitting semiconductor layer into a plurality of microarray-type light emitting regions and a plurality of connect-divided light emitting regions. The multilayered transparent contact layer includes a first transparent contact layer that is composed of a material having a resistance value which is heat determinable, and that divides the plane of the light emitting semiconductor layer into the plurality of microarray-type light emitting regions; a transparent resistor layer that is defined within the first transparent contact layer, that is composed of the material having a resistance value which is heat determinable and has a resistance that is higher than that of the first transparent contact layer; and a second transparent contact layer to connect the plurality of microarray-type light emitting regions.Type: GrantFiled: May 16, 2012Date of Patent: May 26, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventor: Sung Bum Bae
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Publication number: 20150087142Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.Type: ApplicationFiled: November 26, 2014Publication date: March 26, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jong-Won LIM, Ho Kyun AHN, Young Rak PARK, Dong Min KANG, Woo Jin CHANG, Seong-il KIM, Sung Bum BAE, Sang-Heung LEE, Hyung Sup YOON, Chull Won JU, Jae Kyoung MUN, Eun Soo NAM
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Patent number: 8941231Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.Type: GrantFiled: July 10, 2013Date of Patent: January 27, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Young Rak Park, Sang Choon Ko, Byoung-Gue Min, Jong-Won Lim, Hokyun Ahn, Sung-Bum Bae, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 8937002Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.Type: GrantFiled: March 31, 2014Date of Patent: January 20, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Sung Bum Bae, Eun Soo Nam, Jae Kyoung Mun, Sung Bock Kim, Hae Cheon Kim, Chull Won Ju, Sang Choon Ko, Jong-Won Lim, Ho Kyun Ahn, Woo Jin Chang, Young Rak Park
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Publication number: 20140363937Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.Type: ApplicationFiled: June 18, 2014Publication date: December 11, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Woo Jin CHANG, Jong-Won LIM, Ho Kyun AHN, Sang Choon KO, Sung Bum BAE, Chull Won JU, Young Rak PARK, Jae Kyoung MUN, Eun Soo NAM
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Publication number: 20140225121Abstract: Provided are an aluminum gallium nitride template and a fabrication method thereof. The fabrication method includes forming an aluminum nitride (AlN) layer on a substrate, forming a first aluminum gallium nitride (AlxGa1-xN) layer on the aluminum nitride (AlN) layer, forming a second aluminum gallium nitride (AlyGa1-yN) layer on the first aluminum gallium nitride (AlxGa1-xN) layer, forming a third aluminum gallium nitride (AlzGa1-zN) layer on the second aluminum gallium nitride (AlyGal-yN) layer, wherein the first aluminum gallium nitride (AlxGa1-xN) layer, the second aluminum gallium nitride (AlyGa1-yN) layer, and the third aluminum gallium nitride (AlzGa1-zN) layer are formed to have crystal defects and a composition ratio of aluminum (where 1>x>y>z>0) that are gradually decreased as heights of the layers are increased.Type: ApplicationFiled: December 30, 2013Publication date: August 14, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Sung-Bum BAE, Sung Bock KIM, Eun Soo NAM
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Publication number: 20140213045Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.Type: ApplicationFiled: March 31, 2014Publication date: July 31, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Sung Bum BAE, Eun Soo NAM, Jae Kyoung MUN, Sung Bock KIM, Hae Cheon KIM, Chull Won JU, Sang Choon KO, Jong-Won LIM, Ho Kyun AHN, Woo Jin CHANG, Young Rak PARK
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Patent number: 8772833Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.Type: GrantFiled: August 23, 2012Date of Patent: July 8, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Woo Jin Chang, Jong Won Lim, Ho Kyun Ahn, Sang Choon Ko, Sung Bum Bae, Chull Won Ju, Young Rak Park, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140179088Abstract: The inventive concept provides methods for manufacturing a semiconductor substrate. The method may include forming a stop pattern surrounding an edge of a substrate, forming a transition layer an entire top surface of the substrate except the stop pattern, and forming an epitaxial semiconductor layer on the transition layer and the stop pattern. The epitaxial semiconductor layer may not be grown from the stop pattern. That is, the epitaxial semiconductor layer may be isotropically grown from a top surface and a sidewall of the transition layer by a selective isotropic growth method, so that the epitaxial semiconductor layer may gradually cover the stop pattern.Type: ApplicationFiled: May 20, 2013Publication date: June 26, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Sung-Bum BAE, Sung Bock Kim, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 8759204Abstract: The inventive concept provides methods for manufacturing a semiconductor substrate. The method may include forming a stop pattern surrounding an edge of a substrate, forming a transition layer an entire top surface of the substrate except the stop pattern, and forming an epitaxial semiconductor layer on the transition layer and the stop pattern. The epitaxial semiconductor layer may not be grown from the stop pattern. That is, the epitaxial semiconductor layer may be isotropically grown from a top surface and a sidewall of the transition layer by a selective isotropic growth method, so that the epitaxial semiconductor layer may gradually cover the stop pattern.Type: GrantFiled: May 20, 2013Date of Patent: June 24, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Sung-Bum Bae, Sung Bock Kim, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140167070Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.Type: ApplicationFiled: July 10, 2013Publication date: June 19, 2014Inventors: Young Rak PARK, Sang Choon Ko, Byoung-Gue Min, Jong-Won Lim, Hokyun Ahn, Sung-Bum Bae, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 8723222Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.Type: GrantFiled: July 13, 2012Date of Patent: May 13, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Sung Bum Bae, Eun Soo Nam, Jae Kyoung Mun, Sung Bock Kim, Hae Cheon Kim, Chull Won Ju, Sang Choon Ko, Jong-Won Lim, Ho Kyun Ahn, Woo Jin Chang, Young Rak Park
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Publication number: 20130087763Abstract: The inventive concept provides light emitting diodes and methods of manufacturing the same. The light emitting diode may include a first electrode layer, a light emitting layer on the first electrode layer, a second electrode layer on the light emitting layer, and a buffer layer formed on the second electrode layer, the buffer layer having concave-convex patterns increasing extraction efficiency of light generated from the light emitting layer.Type: ApplicationFiled: September 11, 2012Publication date: April 11, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sung Bock Kim, Sung-Bum Bae
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Publication number: 20130069173Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.Type: ApplicationFiled: August 23, 2012Publication date: March 21, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Woo Jin CHANG, Jong Won LIM, Ho Kyun AHN, Sang Choon KO, Sung Bum BAE, Chull Won JU, Young Rak PARK, Jae Kyoung MUN, Eun Soo NAM
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Publication number: 20130069127Abstract: A method for fabricating a field effect transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a cap layer, an ohmic metal layer and an insulating layer on a substrate; forming multilayered photoresists on the insulating layer; patterning the multilayered photoresists to form a photoresist pattern including a first opening for gate electrode and a second opening for field electrode; etching the insulating layer by using the photoresist pattern as an etching mask so that the insulating layer in the first opening is etched more deeply and the cap layer is exposed through the first opening; etching the cap layer exposed by etching the insulating layer through the first opening to form a gate recess region; and depositing a metal on the gate recess region and the etched insulating layer to form a gate-field electrode layer.Type: ApplicationFiled: July 24, 2012Publication date: March 21, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ho Kyun AHN, Jong-Won Lim, Sung Bum Bae, Sang Choon Ko, Young Rak Park, Woo Jin Chang, Jae Kyoung Mun, Eun Soo Nam, Jeong Jin Kim, Chull Won Ju
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Publication number: 20130020649Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.Type: ApplicationFiled: July 13, 2012Publication date: January 24, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sung Bum BAE, Eun Soo NAM, Jae Kyoung MUN, Sung Bock KIM, Hae Cheon KIM, Chull Won JU, Sang Choon KO, Jong-Won LIM, Ho Kyun AHN, Woo Jin CHANG, Young Rak PARK