Patents by Inventor Sung CHEN

Sung CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11490693
    Abstract: A method for assembling a shoe upper and a bottom unit includes digitally determining a bite line on the shoe upper. The method further includes storing a set of data representing the bite line in a computing device. The method also includes utilizing the set of data to automatically indicate the location of an actual physical bite line on the shoe upper.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 8, 2022
    Assignee: NIKE, Inc.
    Inventors: Chiung Li Chang, Yu-Sung Chen, Chih-Hung Chiang
  • Patent number: 11488657
    Abstract: A memory having a plurality of blocks is coupled with control circuits having logic to execute a no-current read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks while disabling current flow. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include, respectively, a plurality of sub-blocks. The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: November 1, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Jen-Hung Huang, Han-Sung Chen
  • Publication number: 20220336006
    Abstract: A memory having a plurality of blocks is coupled with control circuits having logic to execute a no-current read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks while disabling current flow. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include, respectively, a plurality of sub-blocks. The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks.
    Type: Application
    Filed: April 19, 2021
    Publication date: October 20, 2022
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Jen-Hung HUANG, Han-Sung CHEN
  • Patent number: 11475954
    Abstract: A memory having a plurality of blocks is coupled with control circuits having logic to execute a read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include respectively a plurality of sub-blocks, The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: October 18, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Han-Sung Chen, Chung-Kuang Chen
  • Publication number: 20220276559
    Abstract: A positive photosensitive resin composition for a low-temperature process includes an alkali-soluble phenolic resin, a compound with quinonediazide group, a mixed solvent and at least one additive. The mixed solvent includes a first solvent and a second solvent. The first solvent has a volatilization rate of more than 50 relative to a volatilization rate of butyl acetate of 100, and the second solvent has a boiling point between 150° C. and 200° C. The at least one additive has a molecular weight of 500-5000 and a structural unit as Formula (I), wherein R1 is selected from a group consisting of hydrogen, hydroxyl group, C1-C5 alkyl group, phenyl group, halogen atoms and cyano group, R2 is selected from a group consisting of hydrogen, acid radical, benzene and derivatives thereof, phenols, benzoic acid and derivatives thereof and aromatic heterocycles, and n is 10-80.
    Type: Application
    Filed: February 25, 2022
    Publication date: September 1, 2022
    Inventors: Kuan-Ming Chen, Chi-Yu Lai, Chi-sung Chen
  • Publication number: 20220252508
    Abstract: A light emitting apparatus has a plurality of light emitting units, and each of them emits a light with a light emission peak wavelength and a wavelength range. The wavelength ranges of the two light emitting units with the two adjacent light emission peak wavelengths are partially overlapped or non-overlapped. Each of the light emitting units discontinuously emits a light with a lighting frequency. The present disclosure further provides the spectrometer, a light emitting method and a spectrum detection method, and all of them utilizes the light emitting apparatus, a background noise is discarded and a frequency domain signal of an optical spectrum signal of a tested object is reserved, so as to have a filtering effect and achieve high test accuracy, which can replace conventional spectrometer for wavelength resolution characteristics.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 11, 2022
    Inventors: Yi-Sheng TING, Yu-Tsung CHEN, Po-Sung CHEN
  • Patent number: 11361120
    Abstract: The present invention relates to a method for processing building information modeling data including the following steps: inputting a building information model's data that includes two types of multiple objects; identifying the objects to generate results of identification; dividing the objects into a first category and a second category in accordance with the results of identification; removing the objects of the second category; readjusting the first category of objects in accordance with a predetermined rule of a building energy simulation software; and defining attributes of the objects of the first category.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: June 14, 2022
    Assignee: RUENTEX ENGINEERING & CONSTRUCTION CO., LTD.
    Inventors: Samuel Yin, Wu-Sung Chen, Jui-Chen Wang, Ming-Huang Lin, Wen-Kuei Chang
  • Publication number: 20220157379
    Abstract: A memory having a plurality of blocks is coupled with control circuits having logic to execute a read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include respectively a plurality of sub-blocks, The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks.
    Type: Application
    Filed: January 20, 2021
    Publication date: May 19, 2022
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Han-Sung CHEN, Chung-Kuang CHEN
  • Patent number: 11282581
    Abstract: A memory device has a plurality of blocks of memory cells and a plurality of bit lines, each block including a group of word lines, and a set of NAND strings. Each block in the plurality of blocks of memory cells has a plurality of sub-blocks, each sub-block including a distinct subset of the set of NAND strings of the block selected, and a respective sub-block string select line. Control circuits are configured to execute a program operation including applying word line voltages and string select line voltages at a precharge level to precharge the set of NAND strings in the selected block, then lowering the gate voltages on all the sub-block string select lines of the block, and then lowering the word line voltages on the group of word lines. Thereafter, the program of cells in a selected sub-block is executed.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 22, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Han-Sung Chen, Chien-Fu Huang
  • Publication number: 20220077611
    Abstract: A power supply device includes a housing, a circuit board and a conductive spring contact. The housing has a receiving structure. The circuit board is disposed in the housing. The conductive spring contact is disposed in the receiving structure and includes a base portion, a contact portion and a curved portion. The contact portion is connected to the base portion and is bent relative to the base portion. The contact portion extends between the circuit board and a wall portion of the receiving structure, and the contacts the circuit board. The curved portion is connected to the contact portion and abuts against the wall portion.
    Type: Application
    Filed: April 14, 2021
    Publication date: March 10, 2022
    Inventor: Tsun-Sung CHEN
  • Publication number: 20210288572
    Abstract: A low-power-consumption protection circuit includes a load detection module, a secondary feedback control module, and a primary control module. The load detection module is coupled to a current detection unit. The secondary feedback control module is coupled to the load detection module and an isolation unit. The primary control module is coupled to the isolation unit and an isolation switch. When the load detection module detects that the current detection unit outputs a voltage level, the secondary feedback control module transmits a protection signal to the primary control module through the isolation unit.
    Type: Application
    Filed: April 28, 2020
    Publication date: September 16, 2021
    Inventors: Fu-Sung Chen, Chi-Chun Chen
  • Patent number: 11121621
    Abstract: A low-power-consumption protection circuit includes a load detection module, a secondary feedback control module, and a primary control module. The load detection module is coupled to a current detection unit. The secondary feedback control module is coupled to the load detection module and an isolation unit. The primary control module is coupled to the isolation unit and an isolation switch. When the load detection module detects that the current detection unit outputs a voltage level, the secondary feedback control module transmits a protection signal to the primary control module through the isolation unit.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: September 14, 2021
    Assignee: CHICONY POWER TECHNOLOGY CO., LTD.
    Inventors: Fu-Sung Chen, Chi-Chun Chen
  • Patent number: 10992234
    Abstract: A circuit for controlling a power converter includes an SR switching device, a light load detection circuit generating a load detection signal in response to a conduction signal and an operation mode signal, and an SR driver generating a control signal having a value according to the load detection signal and provide the control signal to the SR switching device. A method of controlling a power converter includes generating a load detection signal in response to a conduction signal and an operation mode signal and generating a control signal having a value according to the load detection signal. The control signal has a first value when the load detection signal is asserted and has a second value when the load detection signal is de-asserted.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: April 27, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Sangcheol Moon, Jintae Kim, Chi-Chen Chung, Cheng-Sung Chen
  • Publication number: 20210109998
    Abstract: The present invention relates to a method and a system for processing building energy information. The method includes the following steps: inputting data of a building information model into building energy simulation software; automatically selecting a building category or manually selecting a building category from a group of building categories provided by the building energy simulation software; in response to the selected building category, inputting a plurality of parameters into a lookup table of the building energy simulation software in accordance with a database of the building energy simulation software; and generating an estimation of a building's energy consumption through a calculation by the building energy simulation software based on the parameters.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 15, 2021
    Inventors: Samuel YIN, Wu-Sung CHEN, Jui-Chen WANG, Ming-Huang LIN, Wen-Kuei CHANG
  • Publication number: 20210064710
    Abstract: The present invention relates to a method for processing building information modeling data including the following steps: inputting a building information model's data that includes two types of multiple objects; identifying the objects to generate results of identification; dividing the objects into a first category and a second category in accordance with the results of identification; removing the objects of the second category; readjusting the first category of objects in accordance with a predetermined rule of a building energy simulation software; and defining attributes of the objects of the first category.
    Type: Application
    Filed: October 9, 2019
    Publication date: March 4, 2021
    Inventors: Samuel YIN, Wu-Sung CHEN, Jui-Chen WANG, Ming-Huang LIN, Wen-Kuei CHANG
  • Patent number: 10790009
    Abstract: A memory device comprises a memory cell array, a plurality of sense amplifiers and a memory controller for controlling the plurality of sense amplifiers. The memory cell array includes a plurality of bit lines, where a bit line is coupled to a plurality of memory cells. A sense amplifier is coupled to a bit line and provides a sensing current to access data from one or more memory cells of the plurality of memory cells corresponding to the bit line. The memory controller performs operations comprising: during a pre-charging stage of a memory access cycle, providing, to a particular sense amplifier, a first voltage; and during a sensing stage of the memory access cycle, providing, to the particular sense amplifier, a second voltage, where the second voltage is a non-zero voltage that is lower than the first voltage.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: September 29, 2020
    Assignee: Macronix International Co., Ltd.
    Inventors: Chung-Kuang Chen, Han-Sung Chen
  • Patent number: 10650887
    Abstract: A first read operation is performed using a first voltage level to read data from a memory array. An instant bit count corresponding to a number of bits in the data read from the memory array is determined. A recorded bit count corresponding to a number of bits in the data that was written at a time of writing the data to the memory array is accessed. A difference between the instant bit count and the recorded bit count is obtained. Conditioned on determining that the difference is less than or equal to a first threshold value, the data read from the memory array is output using the first read operation. Conditioned on determining that the difference is greater than the first threshold value, a second read operation is performed using a second voltage level that is distinct from the first voltage level.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: May 12, 2020
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun Hsiung Hung, Han Sung Chen, Ming Chao Lin
  • Patent number: 10641505
    Abstract: A thermal equilibrium for building and an energy-saving air-conditioning system using the same incorporates a first energy-recovery apparatus and a second energy-recovery apparatus. The first energy-recovery apparatus includes a first water storage tank, a foundation pile under and connected to a building architecture construction and a first heat-exchanging pipeline connected to the first water storage tank for performing heat exchange with the foundation pile so that the water in the first heat-exchanging pipeline is heated to a first temperature range. The second energy-recovery apparatus includes a second water storage tank, at least one home appliance that generates a first thermal energy during operation, and a second heat-exchanging pipeline connected to the second water storage tank for performing heat exchange with the at least one home appliance so that the water in the second heat-exchanging pipeline is heated to a second temperature range.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: May 5, 2020
    Assignee: RUENTEX ENGINEERING & CONSTRUCTION CO., LTD.
    Inventors: Samuel Yin, Wu-Sung Chen
  • Patent number: 10637476
    Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: April 28, 2020
    Assignee: Macronix International Co., Ltd.
    Inventors: Chung-Kuang Chen, Chun Hsiung Hung, Han Sung Chen
  • Patent number: 10608544
    Abstract: A Synchronous Rectifier (SR) controller circuit includes a dead time evaluation circuit, an offset voltage controller circuit, an off threshold control circuit, and a comparator circuit. The dead time evaluation circuit produces an indication of whether a measured dead time of an SR switching device is less than a target dead time. The offset voltage controller circuit determines an offset count using the indication, an offset voltage using the offset count, and high and low saturation indicators according to the offset count. The off threshold control circuit determines a threshold count using the high and low saturation indicators and an off threshold voltage using the threshold count. The comparator circuit determines whether a measured voltage of the SR switching device is greater than a virtual off threshold voltage, the virtual off threshold voltage corresponding to the off threshold voltage minus the offset voltage.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: March 31, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Sangcheol Moon, Hangseok Choi, Chi Chen Chung, Cheng-Sung Chen