Patents by Inventor Sung Chung Park

Sung Chung Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080285343
    Abstract: Provided are a memory cell programming method and a semiconductor device which may be capable of simultaneously writing a bit of data and then another bit of the data to a plurality of memory blocks. The memory programming method, in which M bits of data are written to a plurality of memory blocks, may include a data division operation and a data writing operation where M may be a natural number. In the data division operation, the plurality of memory blocks may be divided into a plurality of memory block groups. In the data writing operation, an ith bit of the data may be simultaneously written to two or more memory block groups from among the plurality memory block groups, and then an i+1th bit of the data may be simultaneously written to the two or more memory block groups from among the plurality memory block groups, where i is a natural number less than M.
    Type: Application
    Filed: April 17, 2008
    Publication date: November 20, 2008
    Inventors: Ju-hee Park, Jae-woong Hyun, Yoon-dong Park, Kyoung-lae Cho, Sung-jae Byun, Seung-hwan Song, Jun-jin Kong, Sung-chung Park
  • Publication number: 20080288849
    Abstract: According to an example embodiment, a method of generating a soft decision value using an Analog-to-Digital Converter (ADC) having a given resolution may include receiving metric values calculated based on levels of a transmission signal and output levels of the ADC. Metric values corresponding to a level of a received signal may be selected from among the received metric values. A first maximum metric value may be detected from among the selected metric values when a transmission bit is a first level, and a second maximum metric value may be detected from among the selected metric values when the transmission bit is a second level. The soft decision value may be generated based on a difference between the first maximum metric value and the second maximum metric value.
    Type: Application
    Filed: October 30, 2007
    Publication date: November 20, 2008
    Inventors: Sung Chung Park, Jun Jin Kong, Seung Jae Lee, Seung-Hwan Song
  • Publication number: 20080288853
    Abstract: A code puncturing apparatus and method is provided. The apparatus includes: a codeword selection unit selecting continuous n?1-number of mother codewords from mother codewords generated from k-bit effective information, where k denotes a natural number, and one redundancy bit; and a puncturing unit selecting k-number of redundancy bits from redundancy bits included in the n?1-number of mother codewords, deleting remaining redundancy bits, and rearranging the n?1-number of mother codewords into an n·k bit-target codeword. Accordingly, a code rate of an Error Control Code (ECC) can be raised.
    Type: Application
    Filed: August 13, 2007
    Publication date: November 20, 2008
    Inventors: Jun Jin Kong, Jong Han Kim, Hong Rak Son, Young Hwan Lee, Sung Chung Park, Seung-Hwan Song
  • Publication number: 20080285340
    Abstract: Disclosed are an apparatus and a method for reading data. The method for reading data according to example embodiments includes comparing a threshold voltage of a memory cell with a first boundary voltage, comparing the threshold voltage with a second boundary voltage having a higher voltage level than that of the first boundary voltage, and determining data of the memory cell based on the threshold voltage, the first boundary voltage, and the second boundary voltage.
    Type: Application
    Filed: January 17, 2008
    Publication date: November 20, 2008
    Inventors: Seung-Hwan Song, Jun Jin Kong, Sung Chung Park, Dong Hyuk Chae, Seung Jae Lee, Dong Ku Kang
  • Publication number: 20080276149
    Abstract: An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.
    Type: Application
    Filed: October 3, 2007
    Publication date: November 6, 2008
    Inventors: Jun Jin Kong, Seung-Hwan Song, Young Hwan Lee, Dong Hyuk Chae, Kyoung Lae Cho, Nam Phil Jo, Sung Chung Park, Dong Ku Kang
  • Publication number: 20080276150
    Abstract: An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.
    Type: Application
    Filed: October 3, 2007
    Publication date: November 6, 2008
    Inventors: Jun Jin KONG, Seung-Hwan SONG, Dong Hyuk CHAE, Kyoung Lae CHO, Seung Jae LEE, Nam Phil JO, Sung Chung PARK, Dong Ku KANG
  • Publication number: 20080244339
    Abstract: Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate.
    Type: Application
    Filed: January 18, 2008
    Publication date: October 2, 2008
    Inventors: Jun Jin Kong, Sung Chung Park, Dongku Kang, Dong Hyuk Chae, Seung Jae Lee, Nam Phil Jo, Seung-Hwan Song
  • Publication number: 20080151621
    Abstract: A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream.
    Type: Application
    Filed: May 24, 2007
    Publication date: June 26, 2008
    Inventors: Jun Jin Kong, Sung Chung Park, Dong Ku Kang, Young Hwan Lee, Si Hoon Hong, Jae Woong Hyun
  • Publication number: 20080137413
    Abstract: A multi-level cell (MLC) memory device may include: a MLC memory cell; an outer encoder that encodes data using a first encoding scheme to generate an outer encoded bit stream; and a TCM modulator that applies a program pulse to the MLC memory cell to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream. A method of storing data in a MLC memory device, reading data from the MLC memory device, or storing data in and reading data from the MLC memory device may include: encoding data using a first encoding scheme to generate an outer encoded bit stream; and applying a program pulse to a MLC memory cell of the MLC memory device to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream.
    Type: Application
    Filed: May 22, 2007
    Publication date: June 12, 2008
    Inventors: Jun Jin Kong, Sung Chung Park, Yun Tae Lee, Young Hwan Lee, Si Hoon Hong, Jae Woong Hyun, Dong Ku Kang
  • Publication number: 20080137414
    Abstract: A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.
    Type: Application
    Filed: June 7, 2007
    Publication date: June 12, 2008
    Inventors: Sung Chung Park, Jun Jin Kong, Young Hwan Lee, Dong Ku Kang
  • Publication number: 20080056392
    Abstract: A DCM demapper and a DCM demapping method are provided. The DCM demapper includes: a basic signal generation unit generating a plurality of basic signals using a signal and channel information of two subcarriers; a soft decision generation unit generating a plurality of soft decisions using the plurality of basic signals; and a soft decision selection unit selecting a soft decision corresponding to each bit of the two subcarriers among the generated soft decisions.
    Type: Application
    Filed: February 12, 2007
    Publication date: March 6, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Chung Park, Yun Young Kim, Jun Jin Kong, Jae Ho Roh
  • Publication number: 20060188041
    Abstract: A receiver having a low computation complexity so as to estimate a transmitted includes a likelihood function calculator calculating likelihoods of transmittable signals using a currently received signal, at least one previously received signal, and an estimated signal corresponding to the at least one previously received signal; and a maximum value output unit outputting a transmittable signal corresponding to a likelihood function of the likelihood functions having a maximum value. Thus, a currently received signal can be estimated using a previously received signal, a previously estimated signal, and the currently received signal. As a result, the reliability of the estimated signal can be improved. Also, the previously estimated signal can be stored to prevent the complexity of a computation from being increased.
    Type: Application
    Filed: February 21, 2006
    Publication date: August 24, 2006
    Inventors: Woo-jong Park, Min-seop Jeong, Sung-chung Park, Kwy-ro Lee