Patents by Inventor Sung Dong Cho
Sung Dong Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11887840Abstract: A semiconductor device includes a substrate. A conductive layer is disposed on the substrate and extends in a first direction. An insulating layer is disposed on the conductive layer and exposes at least a portion of the conductive layer through a via hole. The via hole includes a first face extending in a first slope relative to a top face of the conductive layer. A second face extends in a second slope relative to the top face of the conductive layer that is less than the first slope. A redistribution conductive layer includes a first pad area disposed in the via hole. A line area at least partially extends along the first face and the second face. The first face directly contacts the conductive layer. The second face is positioned at a higher level than the first face in a second direction perpendicular to a top face of the substrate.Type: GrantFiled: February 23, 2022Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Sung Kang, Hyoung Yol Mun, Jun U Jin, Bo Hyun Kim, Sung Dong Cho, Won Hee Cho
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Patent number: 11705386Abstract: A semiconductor device includes a substrate, an interlayer insulating layer on the substrate, a first etch stop layer on the substrate, a first through-silicon-via (TSV) configured to pass vertically through the substrate and the interlayer insulating layer, and a second TSV configured to pass vertically through the substrate, the interlayer insulating layer, and the first etch stop layer, wherein the second TSV has a width greater than that of the first TSV.Type: GrantFiled: February 17, 2022Date of Patent: July 18, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang Wuk Park, Sung Dong Cho, Eun Ji Kim, Hak Seung Lee, Dae Suk Lee, Dong Chan Lim, Sang Jun Park
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Publication number: 20230016186Abstract: A semiconductor device includes a substrate. A conductive layer is disposed on the substrate and extends in a first direction. An insulating layer is disposed on the conductive layer and exposes at least a portion of the conductive layer through a via hole. The via hole includes a first face extending in a first slope relative to a top face of the conductive layer. A second face extends in a second slope relative to the top face of the conductive layer that is less than the first slope. A redistribution conductive layer includes a first pad area disposed in the via hole. A line area at least partially extends along the first face and the second face. The first face directly contacts the conductive layer. The second face is positioned at a higher level than the first face in a second direction perpendicular to a top face of the substrate.Type: ApplicationFiled: February 23, 2022Publication date: January 19, 2023Inventors: Min Sung KANG, Hyoung Yol MUN, Jun U JIN, Bo Hyun KIM, Sung Dong CHO, Won Hee CHO
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Publication number: 20220415621Abstract: The present invention relates to a focus ring for improvement of a semiconductor plasma etching process, which is circular, penetrates vertically into the middle portion thereof, and has a plurality of slots equally spaced apart from one another by a given distance on the edge periphery of the underside thereof in a longitudinal direction thereof, wherein so as to allow a plasma to be dispersed and exhausted uniformly at a fast speed through the slots, each slot becomes increased or decreased in diameter in a direction from top to bottom thereof to thus have a top diameter and a bottom diameter different from each other, and otherwise, each slot is rounded inward from both of top and bottom peripheries thereof.Type: ApplicationFiled: August 30, 2022Publication date: December 29, 2022Inventors: Sung Dong CHO, Seung Ho YANG, Seong Wan BAE, Byeong Su AN
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Publication number: 20220173016Abstract: A semiconductor device includes a substrate, an interlayer insulating layer on the substrate, a first etch stop layer on the substrate, a first through-silicon-via (TSV) configured to pass vertically through the substrate and the interlayer insulating layer, and a second TSV configured to pass vertically through the substrate, the interlayer insulating layer, and the first etch stop layer, wherein the second TSV has a width greater than that of the first TSV.Type: ApplicationFiled: February 17, 2022Publication date: June 2, 2022Inventors: Kwang Wuk PARK, Sung Dong CHO, Eun Ji KIM, Hak Seung LEE, Dae Suk LEE, Dong Chan LIM, Sang Jun PARK
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Patent number: 11289402Abstract: A semiconductor device includes a substrate, an interlayer insulating layer on the substrate, a first etch stop layer on the substrate, a first through-silicon-via (TSV) configured to pass vertically through the substrate and the interlayer insulating layer, and a second TSV configured to pass vertically through the substrate, the interlayer insulating layer, and the first etch stop layer, wherein the second TSV has a width greater than that of the first TSV.Type: GrantFiled: November 8, 2019Date of Patent: March 29, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang Wuk Park, Sung Dong Cho, Eun Ji Kim, Hak Seung Lee, Dae Suk Lee, Dong Chan Lim, Sang Jun Park
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Publication number: 20200273780Abstract: A semiconductor device includes a substrate, an interlayer insulating layer on the substrate, a first etch stop layer on the substrate, a first through-silicon-via (TSV) configured to pass vertically through the substrate and the interlayer insulating layer, and a second TSV configured to pass vertically through the substrate, the interlayer insulating layer, and the first etch stop layer, wherein the second TSV has a width greater than that of the first TSV.Type: ApplicationFiled: November 8, 2019Publication date: August 27, 2020Inventors: Kwang Wuk Park, Sung Dong Cho, Eun Ji Kim, Hak Seung Lee, Dae Suk Lee, Dong Chan Lim, Sang Jun Park
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Patent number: 9559002Abstract: A semiconductor device includes a circuit device on a substrate and a first insulating interlayer on the substrate and covering the circuit device. An electrode structure extends through the first insulating interlayer and at least partially through the substrate. An etch-stop layer pattern is disposed on a sidewall of the electrode structure on a side of the first insulating layer opposite the substrate. A blocking layer pattern is disposed on the etch-stop layer pattern. The device further includes an interconnection structure including a via portion passing through the blocking layer pattern to contact the through electrode structure and a wiring portion on the via portion and having a different width than the via portion. The semiconductor device may further include a contact plug electrically connected to the circuit device through the first insulating interlayer. The contact plug and the through electrode structure may include different metals.Type: GrantFiled: July 21, 2015Date of Patent: January 31, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Taek Lee, Eun-Ji Kim, Sin-Woo Kang, Yeong-Lyeol Park, Sung-Dong Cho
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Patent number: 9418915Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a gate structure formed in the interlayer insulating layer, an isolation layer formed in the semiconductor substrate, a through-silicon via formed to penetrate the semiconductor substrate, the interlayer insulating layer, and the isolation layer, and a first conduction type first impurity region coming in contact with the isolation layer and formed to surround only a portion of a sidewall of the through-silicon via in the semiconductor substrate.Type: GrantFiled: October 28, 2014Date of Patent: August 16, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sin-Woo Kang, Sung-Dong Cho
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Patent number: 9293415Abstract: Semiconductor devices including a protection pattern for reducing galvanic corrosion and methods of forming the semiconductor devices are provided. The semiconductor devices may include a substrate including a keep out zone (KOZ) and a plurality of interconnections, which may be disposed outside of the KOZ on the substrate. The semiconductor devices may also include a through silicon via (TSV) in the KOZ. The TSV may pass through the substrate. The semiconductor device may further include a protection pattern, which may be electrically insulated from the TSV, may be disposed in the KOZ and may include a different conductive material from the TSV. A lower end of the protection pattern may be disposed at a level higher than a lower end of the TSV.Type: GrantFiled: May 11, 2015Date of Patent: March 22, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Ji Kim, Sung-Dong Cho, Hyoung-Yol Mun, Yeong-Lyeol Park, Seung-Taek Lee
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Publication number: 20160020145Abstract: A semiconductor device includes a circuit device on a substrate and a first insulating interlayer on the substrate and covering the circuit device. An electrode structure extends through the first insulating interlayer and at least partially through the substrate. An etch-stop layer pattern is disposed on a sidewall of the electrode structure on a side of the first insulating layer opposite the substrate. A blocking layer pattern is disposed on the etch-stop layer pattern. The device further includes an interconnection structure including a via portion passing through the blocking layer pattern to contact the through electrode structure and a wiring portion on the via portion and having a different width than the via portion. The semiconductor device may further include a contact plug electrically connected to the circuit device through the first insulating interlayer. The contact plug and the through electrode structure may include different metals.Type: ApplicationFiled: July 21, 2015Publication date: January 21, 2016Inventors: Seung-Taek Lee, Eun-Ji Kim, Sin-Woo Kang, Yeong-Lyeol Park, Sung-Dong Cho
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Publication number: 20150340314Abstract: Semiconductor devices including a protection pattern for reducing galvanic corrosion and methods of forming the semiconductor devices are provided. The semiconductor devices may include a substrate including a keep out zone (KOZ) and a plurality of interconnections, which may be disposed outside of the KOZ on the substrate. The semiconductor devices may also include a through silicon via (TSV) in the KOZ. The TSV may pass through the substrate. The semiconductor device may further include a protection pattern, which may be electrically insulated from the TSV, may be disposed in the KOZ and may include a different conductive material from the TSV. A lower end of the protection pattern may be disposed at a level higher than a lower end of the TSV.Type: ApplicationFiled: May 11, 2015Publication date: November 26, 2015Inventors: Eun-Ji KIM, Sung-Dong CHO, Hyoung-Yol MUN, Yeong-Lyeol PARK, Seung-Taek LEE
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Publication number: 20150200152Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a gate structure formed in the interlayer insulating layer, an isolation layer formed in the semiconductor substrate, a through-silicon via formed to penetrate the semiconductor substrate, the interlayer insulating layer, and the isolation layer, and a first conduction type first impurity region coming in contact with the isolation layer and formed to surround only a portion of a sidewall of the through-silicon via in the semiconductor substrate.Type: ApplicationFiled: October 28, 2014Publication date: July 16, 2015Inventors: Sin-Woo KANG, Sung-Dong CHO
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Publication number: 20150137388Abstract: A semiconductor device includes a first low-k dielectric layer structure including at least one first low-k dielectric layer sequentially stacked on a substrate, a via structure extending through at least a portion of the substrate and the first low-k dielectric layer structure, and a first blocking layer pattern structure spaced apart from the via structure in the first low-k dielectric layer structure. The first blocking layer pattern structure surrounds a sidewall of the first blocking layer structure.Type: ApplicationFiled: November 20, 2014Publication date: May 21, 2015Inventors: Eun-Ji KIM, Sung-Dong CHO, Sin-Woo KANG, Myung-Soo JANG, Yeong-Lyeol PARK, Seung-Teak LEE
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Patent number: 8890282Abstract: An integrated circuit device includes a substrate having a plurality of device patterns thereon. A device isolation layer is provided on the substrate, an interlayer dielectric layer is provided on the device isolation layer and the substrate, and a conductive via extends through the interlayer dielectric layer and the device isolation layer and into the substrate. A conductive via contact pad is provided on the interlayer dielectric layer in electrical contact with the conductive via. In plan view, the conductive via contact pad is confined within an area of the interlayer dielectric layer and/or an area of the device isolation layer that electrically insulates the conductive via contact pad from the substrate. Related methods and devices are also discussed.Type: GrantFiled: August 29, 2013Date of Patent: November 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Woon-Seob Lee, Sin-Woo Kang, Ki-Young Yun, Sung-Dong Cho, Eun-Ji Kim, Yeong-Lyeol Park
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Patent number: 8841754Abstract: A semiconductor device having a via structure in a stress relief layer is provided. The semiconductor device may include an isolation layer on the circuit region, a stress relief layer on the via region, and a via structure in the stress relief layer and the substrate. The stress relief layer may have a thickness larger than that of the isolation layer and a stepped cross section.Type: GrantFiled: February 8, 2013Date of Patent: September 23, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sin-Woo Kang, Jang-Ho Kim, Woon-Seob Lee, Jong-Hoon Cho, Sung-Dong Cho, Yeong-Lyeol Park
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Patent number: 8836109Abstract: A semiconductor device includes a substrate having a via region and a circuit region, an insulation interlayer formed on a top surface of the substrate, a through electrode having a first surface and a second surface, wherein the through electrode penetrates the via region of the substrate and the second surface is substantially coplanar with a bottom surface of the substrate, a first upper wiring formed on a portion of the first surface of the through electrode, a plurality of via contacts formed on a portion of a top surface of the first upper wiring, and a second upper wiring formed on the plurality of via contacts.Type: GrantFiled: January 30, 2012Date of Patent: September 16, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Young Yun, Yeong-Lyeol Park, Ki-Soon Bae, Woon-Seob Lee, Sung-Dong Cho, Sin-Woo Kang, Sang-Wook Ji, Eun-Ji Kim
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Publication number: 20140225113Abstract: An interposer chip may include a substrate, a plurality of upper terminals, a plurality of lower terminals, a first conductive pattern that electrically connects the first upper terminal to a first set of one or more lower terminals, a second conductive pattern that electrically connects the second upper terminal to a second set of one or more lower terminals and a cut test pattern disposed between the first conductive pattern and the second conductive pattern, the test pattern used for testing electrical characteristics of the first conductive pattern and the second conductive pattern.Type: ApplicationFiled: April 22, 2014Publication date: August 14, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Yeong-Lyeol PARK, Sung-Dong CHO, Sin-Woo KANG
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Patent number: 8729684Abstract: An interposer chip may include a substrate, a plurality of upper terminals, a plurality of lower terminals, a first conductive pattern that electrically connects the first upper terminal to a first set of one or more lower terminals, a second conductive pattern that electrically connects the second upper terminal to a second set of one or more lower terminals and a cut test pattern disposed between the first conductive pattern and the second conductive pattern, the test pattern used for testing electrical characteristics of the first conductive pattern and the second conductive pattern.Type: GrantFiled: August 23, 2011Date of Patent: May 20, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Yeong-Lyeol Park, Sung-Dong Cho, Sin-Woo Kang
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Publication number: 20140124951Abstract: An integrated circuit device includes a substrate having a plurality of device patterns thereon. A device isolation layer is provided on the substrate, an interlayer dielectric layer is provided on the device isolation layer and the substrate, and a conductive via extends through the interlayer dielectric layer and the device isolation layer and into the substrate. A conductive via contact pad is provided on the interlayer dielectric layer in electrical contact with the conductive via. In plan view, the conductive via contact pad is confined within an area of the interlayer dielectric layer and/or an area of the device isolation layer that electrically insulates the conductive via contact pad from the substrate. Related methods and devices are also discussed.Type: ApplicationFiled: August 29, 2013Publication date: May 8, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Woon-Seob Lee, Sin-Woo Kang, Ki-Young Yun, Sung-Dong Cho, Eun-Ji Kim, Yeong-Lyeol Park