Abstract: A semiconductor device may include a substrate and a through electrode. The substrate may have a first surface and a second surface opposite to the first surface, the substrate including circuit patterns formed on the first surface. The through electrode penetrates the substrate and may be electrically connected to the circuit pattern, the through electrode including a first plug that extends from the first surface in a thickness direction of the substrate and a second plug that extends from the second surface in the thickness direction of the substrate so as to be connected to the first plug.

Abstract: A semiconductor device having a via structure in a stress relief layer is provided. The semiconductor device may include an isolation layer on the circuit region, a stress relief layer on the via region, and a via structure in the stress relief layer and the substrate. The stress relief layer may have a thickness larger than that of the isolation layer and a stepped cross section.

Abstract: In an exemplary method of inspecting a stack chip package, a first chip is prepared. The first chip includes a through-silicon via, first pad electrodes connected to the through-silicon via and probe pad electrodes connected to the through-silicon via. A testing chip is prepared. The testing chip includes second pad electrodes that are arranged to correspond with the first pad electrodes. The testing chip is temporarily adhered to the first chip such that the second pad electrodes are electrically connected to the first pad electrode respectively, to form a stack structure wherein the probe pad electrodes are exposed to for testing. An electrical signal is applied to the exposed probe pad electrodes to test the through-silicon via included in the first chip.

Abstract: A semiconductor device includes a substrate having a via region and a circuit region, an insulation interlayer formed on a top surface of the substrate, a through electrode having a first surface and a second surface, wherein the through electrode penetrates the via region of the substrate and the second surface is substantially coplanar with a bottom surface of the substrate, a first upper wiring formed on a portion of the first surface of the through electrode, a plurality of via contacts formed on a portion of a top surface of the first upper wiring, and a second upper wiring formed on the plurality of via contacts.

Abstract: A semiconductor device may include a substrate and a through electrode. The substrate may have a first surface and a second surface opposite to the first surface, the substrate including circuit patterns formed on the first surface. The through electrode penetrates the substrate and may be electrically connected to the circuit pattern, the through electrode including a first plug that extends from the first surface in a thickness direction of the substrate and a second plug that extends from the second surface in the thickness direction of the substrate so as to be connected to the first plug.

Abstract: An interposer chip may include a substrate, a plurality of upper terminals, a plurality of lower terminals, a first conductive pattern that electrically connects the first upper terminal to a first set of one or more lower terminals, a second conductive pattern that electrically connects the second upper terminal to a second set of one or more lower terminals and a cut test pattern disposed between the first conductive pattern and the second conductive pattern, the test pattern used for testing electrical characteristics of the first conductive pattern and the second conductive pattern.

Abstract: Methods of forming electrical interconnects include forming a copper pattern on a semiconductor substrate and then forming an electrically insulating capping layer on the copper pattern and an interlayer insulating layer on the electrically insulating capping layer. A contact hole is then formed, which extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern. An electroless plating step is then performed to form a copper pattern extension onto the exposed upper surface of the copper pattern. The copper pattern extension may have a thickness that is less than a thickness of the electrically insulating capping layer, which may be formed as a SiCN layer.

Abstract: Methods of forming a contact pad include forming a copper pattern on a semiconductor substrate and forming a passivation layer on the copper pattern. The passivation layer is defined to have an opening therein that exposes at least a portion of an upper surface of the copper pattern. A diffusion barrier layer is formed in the opening by electroless plating the diffusion barrier layer onto the exposed portion of the upper surface of the copper pattern. This diffusion barrier layer operates as a barrier to copper out-diffusion from the copper pattern. These methods further include conformally depositing an underbump metallization layer onto at least a sidewall of the opening in the passivation layer and onto an upper surface of the diffusion barrier layer. A step is then performed to plate a contact bump (e.g., solder bump) onto a portion of the underbump metallization layer extending opposite the diffusion barrier layer.

Abstract: Methods of forming electrical interconnects include forming a copper pattern on a semiconductor substrate and then forming an electrically insulating capping layer on the copper pattern and an interlayer insulating layer on the electrically insulating capping layer. A contact hole is then formed, which extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern. An electroless plating step is then performed to form a copper pattern extension onto the exposed upper surface of the copper pattern. The copper pattern extension may have a thickness that is less than a thickness of the electrically insulating capping layer, which may be formed as a SiCN layer.

Abstract: A polymer/ceramic composite paste for an embedded capacitor includes an organic solvent, a ceramic powder having a particle diameter of not more than 20 ?m dispersed in the organic solvent, a polymer and a hardener. The use of the polymer/ceramic composite paste enables the formation of a dielectric layer having a high dielectric constant. The polymer/ceramic composite paste can be applied by a screen printing technique and is planarized to locally form a polymer/ceramic composite dielectric layer having a thickness of, e.g., up to 20 ?m on a desired region. Accordingly, electrical parasitics resulting from the formation of a capacitor on unwanted regions can be reduced, and the capacitance error can be reduced.

Abstract: A method for ashing a semiconductor device is provided. In the method, the semiconductor substrate, on which a metal interconnection and a photoresist pattern are formed, is processed using H2O, and then, by using a mixture of O2, N2, and H2O. The process is performed at least twice repeatedly. As a result, corrosion of the metal interconnection is inhibited and a bridge caused by conductive polymer is prevented.

Abstract: A method for ashing a semiconductor device is provided. In the method, the semiconductor substrate, on which a metal interconnection and a photoresist pattern are formed, is processed using H2O, and then, by using a mixture of O2, N2, and H2O. The process is performed at least twice repeatedly. As a result, corrosion of the metal interconnection is inhibited and a bridge caused by conductive polymer is prevented.