Patents by Inventor Sung-Feng Yeh

Sung-Feng Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200388563
    Abstract: A semiconductor device and method of manufacture are presented in which a first semiconductor device and second semiconductor device are bonded to a first wafer and then singulated to form a first package and a second package. The first package and second package are then encapsulated with through interposer vias, and a redistribution structure is formed over the encapsulant. A separate package is bonded to the through interposer vias.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Tzuan-Horng Liu
  • Publication number: 20200381379
    Abstract: Provided is a three-dimensional integrated circuit (3DIC) structure including a first die and a second die bonded together by a hybrid bonding structure. One of the first die and the second die has a pad and a cap layer disposed over the pad. The cap layer exposes a portion of a top surface of the pad, and the portion of the top surface of the pad has a probe mark. A bonding metal layer of the hybrid bonding structure penetrates the cap layer to electrically connect to the pad. A method of fabricating the first die or the second die of 3DIC structure is also provided.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Sung-Feng Yeh
  • Publication number: 20200381397
    Abstract: A package includes a first device die, and a second device die bonded to the first device die through hybrid bonding. The second device die is larger than the first device die. A first isolation region encapsulates the first device die therein. The first device die, the second device die, and the first isolation region form parts of a first package. A third device die is bonded to the first package through hybrid bonding. The third device die is larger than the first package. A second isolation region encapsulates the first package therein. The first package, the third device die, and the second isolation region form parts of a second package.
    Type: Application
    Filed: October 1, 2019
    Publication date: December 3, 2020
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen
  • Publication number: 20200381396
    Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.
    Type: Application
    Filed: September 3, 2019
    Publication date: December 3, 2020
    Inventors: Ming-Fa Chen, Tzuan-Horng Liu, Chao-Wen Shih, Sung-Feng Yeh, Nien-Fang Wu
  • Patent number: 10854574
    Abstract: A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Sung-Feng Yeh, Wen-Chih Chiou
  • Patent number: 10840217
    Abstract: A chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, and the dielectric layer is substantially made of a semiconductor oxide material. The chip package further includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Sung-Feng Yeh
  • Publication number: 20200343218
    Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chia Hu, Ming-Fa Chen, Sung-Feng Yeh
  • Publication number: 20200343223
    Abstract: A package structure includes a first semiconductor die, a second semiconductor die, an insulating encapsulant and a redistribution layer. The first semiconductor die has first conductive posts and a first protection layer laterally surrounding the first conductive posts. The second semiconductor die is embedded in the first protection layer and surrounded by the first conductive posts of the first semiconductor die, wherein the second semiconductor die includes second conductive posts. The insulating encapsulant is encapsulating the first semiconductor die and the second semiconductor die. The redistribution layer is disposed on the insulating encapsulant and connected with the first conductive posts and the second conductive posts, wherein the first semiconductor die is electrically connected with the second semiconductor die through the first conductive posts, the redistribution layer and the second conductive posts.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Sung-Feng Yeh, Chao-Wen Shih
  • Patent number: 10797015
    Abstract: A method of manufacturing a 3DIC structure includes the following processes. A die is bonded to a wafer. A first dielectric layer is formed on the wafer and laterally aside the die. A second dielectric material layer is formed on the die and the first dielectric layer. A portion of the second dielectric material layer over a non-edge region of the wafer is selectively removed to form a protruding portion over an edge region of the wafer. The second dielectric material layer is planarized to form a second dielectric layer on the first dielectric layer and the die. A bonding film is formed on the second dielectric layer. A carrier is bonded to the wafer through the bonding film.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Feng Yeh, Hsien-Wei Chen, Ming-Fa Chen
  • Publication number: 20200312758
    Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.
    Type: Application
    Filed: June 15, 2020
    Publication date: October 1, 2020
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen
  • Publication number: 20200303301
    Abstract: The present disclosure provides a semiconductor package, including a first semiconductor structure, including an active region in a first substrate portion, wherein the active region includes at least one of a transistor, a diode, and a photodiode, a first bonding metallization over the first semiconductor structure, a first bonding dielectric over the first semiconductor structure, surrounding and directly contacting the first bonding metallization, a second semiconductor structure over a first portion of the first semiconductor structure, a second bonding metallization at a front surface of the second semiconductor structure, a second bonding dielectric surrounding and directly contacting the second bonding metallization, a conductive through via over a second portion of the first semiconductor structure different from the first portion, and a passive device directly over the conductive through via.
    Type: Application
    Filed: June 12, 2020
    Publication date: September 24, 2020
    Inventors: MING-FA CHEN, SUNG-FENG YEH, CHEN-HUA YU
  • Patent number: 10784219
    Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ching-Pin Yuan, Sung-Feng Yeh, Sen-Bor Jan, Ming-Fa Chen
  • Publication number: 20200294870
    Abstract: In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Hui-Wen Liu, Ching-Pin Yuan
  • Publication number: 20200294984
    Abstract: A package manufacturing having a semiconductor substrate, a bonding layer, at least one semiconductor device, a redistribution circuit structure and an insulating encapsulation. The bonding layer is disposed on the semiconductor substrate. The semiconductor device is disposed on and in contact with a portion of the bonding layer, wherein the bonding layer is located between the semiconductor substrate and the semiconductor device and adheres the semiconductor device onto the semiconductor substrate. The redistribution circuit structure is disposed on and electrically connected to the semiconductor device, wherein the semiconductor device is located between the redistribution circuit structure and the bonding layer. The insulating encapsulation wraps a sidewall of the semiconductor device, wherein a sidewall of the bonding layer is aligned with a sidewall of the insulating encapsulation and a sidewall of the redistribution circuit structure.
    Type: Application
    Filed: May 31, 2020
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Sung-Feng Yeh, Chi-Hwang Tai
  • Publication number: 20200279831
    Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant, an isolation layer and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive post disposed on the semiconductor substrate. The insulating encapsulant is partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant. The isolation layer is disposed on the insulating encapsulant and surrounding the second portion of the conductive post. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 10756010
    Abstract: A semiconductor device and method of manufacture are presented in which a first semiconductor device and second semiconductor device are bonded to a first wafer and then singulated to form a first package and a second package. The first package and second package are then encapsulated with through interposer vias, and a redistribution structure is formed over the encapsulant. A separate package is bonded to the through interposer vias.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Tzuan-Horng Liu
  • Patent number: 10685935
    Abstract: A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Sung-Feng Yeh, Wen-Chih Chiou
  • Patent number: 10685911
    Abstract: The present disclosure provides a semiconductor package, including a first semiconductor structure, a first bonding dielectric over the first semiconductor structure and surrounding a first bonding metallization structure, a through via over the first bonding dielectric, and a passive device passive device electrically coupled to the through via and the first bonding metallization structure. The present disclosure also provides a method for manufacturing a semiconductor package, including providing a first die, bonding a second die with the first die, wherein the second die partially covers the first die thereby forming a gap over an uncovered portion of the first die, filling the gap over the first die with dielectric, forming a through dielectric via (TDV) in the filled gap, and forming a passive device over the second die and the TDV.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Chen-Hua Yu
  • Patent number: 10685910
    Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen
  • Publication number: 20200185330
    Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.
    Type: Application
    Filed: April 1, 2019
    Publication date: June 11, 2020
    Inventors: Chen-Hua Yu, Tzuan-Horng Liu, Ming-Fa Chen, Chao-Wen Shih, Sung-Feng Yeh