Abstract: A semiconductor structure and a method for forming the same are provided. The method comprises: providing a first semiconductor workpiece; bonding a second semiconductor workpiece to a first surface of the first semiconductor workpiece; forming a first electrically conductive via through the second semiconductor workpiece to the first semiconductor workpiece; bonding a third semiconductor workpiece to a second surface of the first semiconductor workpiece, the second surface being opposite to the first surface; and forming a second electrically conductive via through the first semiconductor workpiece and the third semiconductor workpiece to the second semiconductor workpiece such that the first electrically conductive via and the second electrically conductive via are electrically connected.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes: providing a first semiconductor workpiece; depositing a first film on a first surface of the semiconductor workpiece; depositing a second film on a substrate that is transmissive to light within a predetermined wavelength range; and bonding the first film to the second film under a predetermined bonding temperature and a predetennined bonding pressure.

Abstract: An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

Abstract: A chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, and the dielectric layer is substantially made of a semiconductor oxide material. The chip package further includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip.

Abstract: Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first chip, a second chip and at least one through substrate via (TSV). The first chip is electrically connected to the second chip with a first bonding pad of the first chip and a second bonding pad of the second chip. The TSV extends from a first backside of the first chip to a metallization element of the first chip. At least one conductive via is electrically connected between the TSV and the first bonding pad, and at least one elongated slot or closed space is within the at least one conductive via.

Abstract: Provided is a 3DIC structure including first and second IC chips and connectors. The first IC chip includes a first metallization structure, a first optical active component, and a first photonic interconnection layer. The second IC chip includes a second metallization structure, a second optical active component, and a second photonic interconnection layer. The first and second IC chips are bonded via the first and second photonic interconnection layers. The first optical active component is between the first photonic interconnection layer and the first metallization structure. The first optical active component and the first metallization structure are bonded to each other. The second optical active component is between the second photonic interconnection layer and the second metallization structure. The second optical active component and the second metallization structure are bonded to each other.

Abstract: Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first chip, a second chip and at least one through substrate via (TSV). The first chip is electrically connected to the second chip with a first bonding pad of the first chip and a second bonding pad of the second chip. The TSV extends from a first backside of the first chip to a metallization element of the first chip. At least one conductive via is electrically connected between the TSV and the first bonding pad, and at least one elongated slot or closed space is within the at least one conductive via.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a non-rectangular die area, a dicing ring and a reticle area surrounding the non-rectangular die. The dicing ring is within the reticle area and surrounds the non-rectangular die area. The number of edges of the reticle area is not equal to 4.

Abstract: An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

Abstract: Semiconductor dies are bonded to each other and electrically connected to each other. An encapsulant is utilized to protect the semiconductor dies and external connections are formed to connect the semiconductor dies within the encapsulant. In an embodiment the external connections may comprise conductive pillars, conductive reflowable material, or combinations of such.

Abstract: A package according to an embodiment includes a first device package and a fan-out RDL disposed over the first device package. The fan-out RDL extends past edges of the first device package. The first device package comprises a first die having a first redistribution layer (RDL) disposed on a first substrate, a second die having a second RDL disposed on a second substrate, an isolation material over the first die and extending along sidewalls of the second die, and a conductive via. The first RDL is bonded to the second RDL, and the first die and the second die comprise different lateral dimensions. At least a portion of the conductive via extends from a top surface of the isolation material to contact a first conductive element in the first RDL.

Abstract: A package according to an embodiment includes a first device package and a fan-out RDL disposed over the first device package. The fan-out RDL extends past edges of the first device package. The first device package comprises a first die having a first redistribution layer (RDL) disposed on a first substrate, a second die having a second RDL disposed on a second substrate, an isolation material over the first die and extending along sidewalls of the second die, and a conductive via. The first RDL is bonded to the second RDL, and the first die and the second die comprise different lateral dimensions. At least a portion of the conductive via extends from a top surface of the isolation material to contact a first conductive element in the first RDL.

Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.

Abstract: Semiconductor dies are bonded to each other and electrically connected to each other. An encapsulant is utilized to protect the semiconductor dies and external connections are formed to connect the semiconductor dies within the encapsulant. In an embodiment the external connections may comprise conductive pillars, conductive reflowable material, or combinations of such.

Abstract: A package according to an embodiment includes a first device package and a fan-out RDL disposed over the first device package. The fan-out RDL extends past edges of the first device package. The first device package comprises a first die having a first redistribution layer (RDL) disposed on a first substrate, a second die having a second RDL disposed on a second substrate, an isolation material over the first die and extending along sidewalls of the second die, and a conductive via. The first RDL is bonded to the second RDL, and the first die and the second die comprise different lateral dimensions. At least a portion of the conductive via extends from a top surface of the isolation material to contact a first conductive element in the first RDL.

Abstract: A cutting mold for removing two opposite superfluous rigid circuit boards from a rigid-flexible circuit board. A first cutter is connected to a first moldboard. A first barricade is connected to the first moldboard. The maximum vertical distance from the first barricade to the first moldboard exceeds that from the first cutter to the first moldboard. A second moldboard is opposite the first moldboard. The first and second moldboards move with respect to each other. A second cutter is connected to the second moldboard and corresponds to the first cutter. A second barricade is connected to the second moldboard and detachably abuts the first barricade. The maximum vertical distance from the second barricade to the second moldboard exceeds that from the second cutter to the second moldboard. The first and second cutters cut the superfluous rigid circuit boards when the first and second moldboards move toward each other.

Abstract: A cutting mold for removing two opposite superfluous rigid circuit boards from a rigid-flexible circuit board. A first cutter is connected to a first moldboard. A first barricade is connected to the first moldboard. The maximum vertical distance from the first barricade to the first moldboard exceeds that from the first cutter to the first moldboard. A second moldboard is opposite the first moldboard. The first and second moldboards move with respect to each other. A second cutter is connected to the second moldboard and corresponds to the first cutter. A second barricade is connected to the second moldboard and detachably abuts the first barricade. The maximum vertical distance from the second barricade to the second moldboard exceeds that from the second cutter to the second moldboard. The first and second cutters cut the superfluous rigid circuit boards when the first and second moldboards move toward each other.