Abstract: A semiconductor structure includes a first die, a dielectric layer, a second interconnection structure, a second conductive pad and a conductive feature. The first die includes a first interconnection structure over a first substrate and a first conductive pad disposed on and electrically connected to the first interconnection structure. The first conductive pad has a probe mark on a surface thereof. The dielectric layer laterally warps around the first die. The second interconnection structure is disposed on the first die and the dielectric layer, the second interconnection structure includes a conductive via landing on the first conductive pad of the first die, and the conductive via is spaced apart from the first probe mark. The second conductive pad is disposed on and electrically connected to the second interconnection structure. The conductive feature is disposed on the second conductive pad.

Abstract: A chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, and the dielectric layer is substantially made of a semiconductor oxide material. The chip package further includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip.

Abstract: An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.

Abstract: A package includes an integrated circuit. The integrated circuit includes a first chip, a dummy chip, a second chip, and a third chip. The first chip includes a semiconductor substrate that extends continuously from an edge of the first chip to another edge of the first chip. The dummy chip is disposed over the first chip and includes a semiconductor substrate that extends continuously from an edge of the dummy chip to another edge of the dummy chip. Sidewalls of the first chip are aligned with sidewalls of the dummy chip. The second chip and the third chip are sandwiched between the first chip and the dummy chip. A thickness of the second chip is substantially equal to a thickness of the third chip.

Abstract: Embodiments utilize a bridge die that directly bonds to and bridges two or more device dies. Each of the device dies can have additional device dies stacked thereupon. In some embodiments, the bridge die can bridge device dies disposed both under and over the bridge die. In some embodiments, several bridge dies may be used to bridge a device die to other adjacent device dies.

Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

Abstract: An integrated circuit includes a conductive pad. In some embodiments, the conductive pad includes at least one dielectric pattern therein, wherein the at least one dielectric pattern penetrates a surface of the conductive pad. In some embodiments, the conductive pad includes a conductive main body and at least one hole in the conductive main body, wherein the at least one hole penetrates a surface of the conductive main body.

Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.

Abstract: A package includes an integrated circuit. The integrated circuit includes a first chip, a second chip, a third chip, and a fourth chip. The second chip and the third chip are disposed side by side on the first chip. The second chip and the third chip are hybrid bonded to the first chip. The fourth chip is fusion bonded to at least one of the second chip and the third chip.

Abstract: A package structure and a method of fabricating the same are provided. The method includes bonding a first die and a second die to a wafer in a first die region of the wafer hybrid bonding; bonding a first dummy structure to the wafer in the first die region and a first scribe line of the wafer; and singulating the wafer and the first dummy structure along the first scribe line to form a stacked integrated circuit (IC) structure.

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.

Abstract: A semiconductor device and method of manufacture are presented in which a first semiconductor device and second semiconductor device are bonded to a first wafer and then singulated to form a first package and a second package. The first package and second package are then encapsulated with through interposer vias, and a redistribution structure is formed over the encapsulant. A separate package is bonded to the through interposer vias.

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

Abstract: A package device includes a first device die and second device die bonded thereto. When the area of the second device die is less than half the area of the first device die, one or more inactive structures having a semiconductor substrate is also bonded to the first device die so that the combined area of the second device die and the one or more inactive structures is greater than half the area of the first device die.

Abstract: A semiconductor device and method of manufacture are provided wherein the semiconductor device includes a first system on chip device bonded to a first memory device, a second system on chip device bonded to the first memory device, a first encapsulant surrounding the first system on chip device and the second system on chip device, a second encapsulant surrounding the first system on chip device, the second system on chip device, and the first memory device, and a through via extending from a first side of the second encapsulant to a second side of the first encapsulant, the through via being located outside of the first encapsulant.

Abstract: A package structure including a bottom die, a first die, a second die, an encapsulant and a first dummy structure is provided. The first die and a second die are bonded to a first side of the bottom die. The encapsulant laterally encapsulates the first die and the second die. The first dummy structure is bonded to the first side of the bottom die, wherein a sidewall of the first dummy structure is coplanar with a first sidewall of the bottom die.

Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.

Abstract: A semiconductor structure includes a first semiconductor device, a second semiconductor device, a connection device and a redistribution circuit structure. The first semiconductor device is bonded on the second semiconductor device. The connection device is bonded on the second semiconductor device and arranged aside of the first semiconductor device, wherein the connection device includes a first substrate and conductive vias penetrating through the first substrate and electrically connected to the second semiconductor device. The redistribution circuit structure is located over the second semiconductor device, wherein the first semiconductor device and the connection device are located between the redistribution circuit structure and the second semiconductor device. The redistribution circuit structure and the first semiconductor device are electrically connected to the second semiconductor device through the conductive vias of the connection device.