Abstract: A nonvolatile semiconductor integrated circuit having a cell array consisting of a plurality of memory strings each having first to N-th (N=2, 3, 4, . . . ) memory cell transistors of a NAND structure includes a plurality of first string select transistors connected in series to the first memory cell transistor, and a plurality of second string select transistors connected in series to the N-th memory cell transistor. One of the string select transistors serially connected to the first and N-th memory cell transistors has a control terminal connected to a ground connecting point, thus to have a ground select function as well as a string select function.

Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrodes, and an image defect area caused by the impurity ions is screened with the black matrix.

Abstract: A novel sense amplifier circuit is provided that includes a resistor and a reference cell connected in parallel to a reference line. The reference cell is composed of a floating-gate field effect transistor having the same characteristic as a memory cell. The reference cell is programmed so as to have a threshold voltage between the threshold voltages of an associated memory cell transistor in an on-state and an off state. According to this circuit configuration, a reference current is determined only by a current flowing through the resistor, when a gate voltage to a memory/reference cell is higher than the threshold voltage of the reference cell. This forces the reference current to exist between the on-cell current and the off-cell current, regardless of the gate voltage. Therefore, the maximum operating voltage of the sense amplifier circuit according to the invention is not limited by a variation of the gate voltage to the memory/reference cell, or by a variation of a power supply voltage.

Abstract: A lead frame transfer device includes a platform, and front and rear fingers for moving the lead frame from a transfer position to a feeding position, via the platform, with minimal impact and while producing minimal mechanical abrasion. Each of the fingers includes a plate-like support for the lead frame, a vertical cylinder for moving the support in a vertical direction, and a horizontal cylinder for moving the support in a horizontal direction. The device also has a sensor for detecting the presence of a lead frame on the platform, and which detection is used to control the movement of the plate-like supports. A wire bonding apparatus employs two of such transfer devices on either side of a wire bonding head. Transfer rails extend past the transfer devices.

Abstract: A method and appratus for transporting a lead frame on air rails, wherein the lead frame is moved by pressurized air, and an in-line package assembly system using the method and apparatus.

Abstract: A method for preparing spherical phosphor particles is disclosed, wherein a precursor solution of phosphors is decomposed to solid particles by aerosol pyrolysis and rapid cooling and subsequently the solid particles are heat-treated at a temperature of 1000.degree. C. to 1600.degree. C. for a period of 1 hour to 9 hours.

Abstract: A polysilicon gate electrode of an integrated circuit field effect transistor is formed in two portions which are isolated from one another. The first portion is formed on the gate insulating region. The second portion is formed on the semiconductor substrate outside the gate insulating region and is electrically insulated from the first portion. Since the first and second portions of the polysilicon gate electrode are isolated from one another, only the charge which is on the first polysilicon portion contributes to gate insulating region degradation during plasma etching. After polysilicon gate electrode formation, the first and second portions may be electrically connected by a link. Field effect transistor performance and/or reliability are thereby increased.

Abstract: A semiconductor integrated circuit having an address transition detector includes a power detecting circuit connected to a source terminal for detecting a voltage level of the source terminal, a pulse generating circuit for receiving an address signal and generating a pulse when the address signal is changed, and a summator for combining outputs of the power detecting circuit and the pulse generating circuit and generating a given pulse when the outputs vary.

Abstract: An apparatus for serially transferring lead frames from a container containing a plurality of lead frames and buffering materials, which are stacked alternatively, to a die bonding process. The apparatus includes a guide bar provided with first pads for picking up a lead frame and second pads for picking up a sheet of buffering material, the first and second pads being moved concurrently downward and upward and vibrated.

Abstract: A nonvolatile semiconductor memory with a unit cell structure suitable for high speed operation and a low power supply voltage. The nonvolatile semiconductor memory includes a switching circuit including block select transistors connected by its respective terminal to a corresponding bit line. This switching circuit transmits a signal only when a string to which the switching circuit corresponds is selected. A second active region having a different impurity concentration from a first active region constituting source and drain regions of memory transistors is formed at a substrate contact portion of a bit line contact portion where the memory string and bit line are connected. The impurity concentration of the second active region is lower than that of the first active region.

Abstract: A nonvolatile semiconductor memory with a unit cell structure suitable for high speed operation and a low power supply voltage. The nonvolatile semiconductor memory includes a switching circuit including block select transistors connected by its respective terminal to a corresponding bit line. This switching circuit transmits a signal only when a string to which the switching circuit corresponds is selected. A second active region having a different impurity concentration from a first active region constituting source and drain regions of memory transistors is formed at a substrate contact portion of a bit line contact portion where the memory string and bit line are connected. The impurity concentration of the second active region is lower than that of the first active region.

Abstract: A nonvolatile memory device containing sub memory arrays and distinct associated peripheral sub array circuits containing error checking and correction circuits that are similarly positioned according to the sub array. The memory device is configured so that a single mask change allows the device to be manufactured as a normal mode device or a page mode device.

Abstract: A mask ROM having a defect repairing function stores address signals corresponding to a defective memory cell and then, selectively activates either a redundancy row decoder or a row decoder according to whether the address signals stored are identical to address signals supplied externally. The mask ROM includes first and second memory cell arrays formed by grouping in a word line direction a plurality of read only memory cells arranged in rows and columns; first and second row decoders for combining row address signals supplied externally so as to selectively drive the word lines of the first and second memory cell arrays; and a row decoder selector for storing therein address signals according to a row block including a defective memory cell, of the first memory cell array so as to inactivate the first row decoder and activate the second row decoder when the external row address signals are equal to the address signals stored in the row decoder selector.

Abstract: A data output control circuit of a semiconductor memory device. The data output control circuit comprises an input signal detector for detecting a desired signal, a controller for selecting one of a plurality of data output buffers and a data output controller for driving the selected data output buffer. A signal for driving and controlling the data output buffer is enabled after the data of a given memory cell is supplied to an input terminal of the data output buffer so that any unnecessary transition operation of data can be eliminated to reduce the current dissipation of a semiconductor memory chip and to prevent the deterioration of data access time for the purpose of improving the yield of the semiconductor memory chip.

Abstract: A semiconductor memory device which is comprised of a plurality m of electrically isolated data memory sub-arrays for storing data bits and a plurality k of electrically isolated parity memory sub-arrays for storing parity bits, wherein each of the data and parity memory sub-arrays includes a plurality of memory cells arranged in a matrix of rows and columns, with the memory cells in each row connected to a common word line and the memory cells in each column connected to a common bit line. Row address decoders function to activate a selected word line in each of the memory sub-arrays, and column address decoders, in combination with column selection circuitry, function to couple a selected bit line in each of the memory sub-arrays to a plurality m of sense amplifiers, which function to sense the voltage level of respective ones of the selected bit lines, and produce output data and parity bits representative of these sensed voltage levels.

Abstract: A plural test mode selection circuit in a semiconductor device capable of extending the number of option modes, e.g., up to 16 option modes by adding a high voltage sensing circuit 15 to any one of a plurality of input pads and by arranging a master decoder 25 and a slave decoder 20 each coupled to a plurality of buffer circuits 11-14, as well as a mode selector 30 and a plurality of address/control pads 5-9, and then an output of a high voltage sensing circuit 15 and respective outputs of the master decoder 25 and a slave decoder 20 are combined together at a mode selector 30, so that a plurality of test modes selection is possible therefrom. In addition, the invention also has an advantage capable of testing a chip even after it has been made into a package because of utilizing the address/control pad used in a general read/write operation.