Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

Abstract: A semiconductor device includes a substrate having a trench, a bit line in the trench, a first spacer extending along the trench and at least a portion of a side surface of the bit line and in contact with the bit line, and a second spacer disposed within the trench on the first spacer. The bit line is narrower than the trench, and the first spacer includes silicon oxide. A method of forming a semiconductor device includes forming a trench in a substrate, forming a bit line within the first trench of width less than that of the first trench, and forming a first spacer that lines a portion of the trench and includes silicon oxide in contact with at least a portion of a side surface of the bit line, and forming a second spacer over the first spacer in the trench.

Abstract: A semiconductor device includes: a substrate having active regions defined by a device isolation region; a conductive line extending in a direction on the active regions; insulating liners on both sidewalls of a lower portion of the conductive line that contacts with the active regions; spacers that are apart from the insulating liners in a direction perpendicular to a surface of the substrate and sequentially formed on both sidewalls of an upper portion of the conductive line; a blocking layer arranged at a spacing between a spacer located in the middle of the spacers and the insulating liners and in a recess portion recessed from one end of the spacer located in the middle of the spacers toward the conductive line; and conductive patterns arranged on the active regions on both sides of the spacers.

Abstract: A semiconductor memory device according to an example embodiment of the present inventive concept may include: a plurality of lower electrodes located on a substrate and spaced apart from one another; and an etch stop pattern located on the substrate and surrounding at least a part of each of the plurality of lower electrodes, in which the etch stop pattern includes: a first etch stop pattern including carbon; and a second etch stop pattern located on the first etch stop pattern and including a material different from a material of the first etch stop pattern.

Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a cell region and a peripheral region having different active region densities, forming cell trenches for limiting cell active regions in the cell region so that the cell active regions are formed to be spaced apart by a first width in a first direction and by a second width in a second direction, forming peripheral trenches for limiting a peripheral active region in the peripheral region, and forming, in the cell trenches, a first insulating layer continuously extending in the first and second directions and contacting sidewalls of the cell active regions, and having a thickness equal to or greater than half of the first width and less than half of the second width.

Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

Abstract: A semiconductor device includes a substrate including an active region and an element isolation region defining the active region, a gate trench extending into the element isolation region and penetrating the active region, and a gate structure filling the gate trench and including a first conductivity-type semiconductor layer, a conductive layer, and a second conductivity-type semiconductor layer, sequentially stacked from a lower portion of the gate trench.

Abstract: A semiconductor memory device according to an example embodiment of the present inventive concept may include: a plurality of lower electrodes located on a substrate and spaced apart from one another; and an etch stop pattern located on the substrate and surrounding at least a part of each of the plurality of lower electrodes, in which the etch stop pattern includes: a first etch stop pattern including carbon; and a second etch stop pattern located on the first etch stop pattern and including a material different from a material of the first etch stop pattern.

Abstract: A semiconductor device includes a plurality of conductive structures arranged on a substrate and spaced apart from each other in a second direction substantially perpendicular to a first direction, in which each of the plurality of conductive structures extends in the first direction. A plurality of contact structures are arranged between the conductive structures in an alternating arrangement and spaced apart from each other in the first direction. A plurality of insulation structures are arranged in a space between the conductive structures and between the contact structures. A plurality of air spacers are arranged between the alternating arrangement of the plurality of conductive structures and the plurality of contact structures, respectively and spaced apart from each other in the first direction.

Abstract: Disclosed is a vehicle door latch.

Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

Abstract: A semiconductor device includes a substrate having a trench, a bit line in the trench, a first spacer extending along the trench and at least a portion of a side surface of the bit line and in contact with the bit line, and a second spacer disposed within the trench on the first spacer. The bit line is narrower than the trench, and the first spacer includes silicon oxide. A method of forming a semiconductor device includes forming a trench in a substrate, forming a bit line within the first trench of width less than that of the first trench, and forming a first spacer that lines a portion of the trench and includes silicon oxide in contact with at least a portion of a side surface of the bit line, and forming a second spacer over the first spacer in the trench.

Abstract: A semiconductor device includes a substrate including an active region and an element isolation region defining the active region, a gate trench extending into the element isolation region and penetrating the active region, and a gate structure filling the gate trench and including a first conductivity-type semiconductor layer, a conductive layer, and a second conductivity-type semiconductor layer, sequentially stacked from a lower portion of the gate trench.

Abstract: The present inventive concept provides, for an optical modulation unit of which the manufacturing is simplified and the performance is improved and a stereoscopic display having the same, an optical modulation unit and a stereoscopic display device comprising the same, the optical modulation unit comprising: a liquid crystal cell having different phase delay amounts of penetrated light in the on and off states; and a phase delay film part arranged on at least one among an optical path of light having passed through the liquid crystal cell and an optical path of light entering into the liquid crystal cell, and comprising a phase delay film having a fixed phase delay amount, wherein when a wavelength of light, which has passed through both the liquid crystal cell and the phase delay film part, is ?, a phase delay amount of the light having passed through both the liquid crystal cell and the phase delay film part is ?/4 when the liquid crystal cell is in the on state and ??/4 when the liquid crystal cell is in t

Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.

Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.

Abstract: A semiconductor device, including an active region defined in a semiconductor substrate; a first contact plug on the semiconductor substrate, the first contact plug being connected to the active region; a bit line on the semiconductor substrate, the bit line being adjacent to the first contact plug; a first air gap spacer between the first contact plug and the bit line; a landing pad on the first contact plug; a blocking insulating layer on the bit line; and an air gap capping layer on the first air gap spacer, the air gap capping layer vertically overlapping the first air gap spacer, the air gap capping layer being between the blocking insulating layer and the landing pad, an upper surface of the blocking insulating layer being at a height equal to or higher than an upper surface of the landing pad.

Abstract: Disclosed is a protection device for a blind string. The protection device includes a bellows tube provided in a tubular structure, allowing the blind string to pass through an inner part thereof, and having a length increased or reduced in a longitudinal direction of the blind string, a first module coupled with a lower end portion of the bellows tube and having an inner part to which an end portion of the blind string is locked, and a second module decoupled from the first module at an upper portion of the first module while the bellows tube is interposed between the first module and the second module, such that the bellows tube is folded. The bellows tube has a difference in the thickness of the skin thereof such that the bellows tube is automatically spread due to elasticity thereof when the second module is moved up from the first module.

Abstract: A semiconductor device includes a substrate with an active pattern, the active pattern having a first extension portion extending in a first direction substantially parallel to a top surface of the substrate, a second extension portion extending from a first end of the first extension portion in a third direction oriented obliquely to the first direction, a third extension portion extending from a second end of the first extension portion in a direction opposed to the third direction, a first projection portion protruding from the second extension portion in a direction opposed to the first direction, the first projection portion being spaced apart from the first extension portion, and a second projection portion protruding from the third extension portion in the first direction, the second projection portion being spaced apart from the first extension portion.