Abstract: Disclosed is an apparatus for removing a thermal sleeve from a cold leg of a reactor coolant system, which removes an unintentionally separated thermal sleeve without pipe cutting, preventing invasion of impurities into pipes and achieving reliable pipe re-welding. The apparatus includes a sleeve removal tool including a corn head formed at a shaft, a pressure plate below the corn head to maximize hydraulic pressure inside a safety injection pipe, a spring connected to the pressure plate to keep the pressure plate unfolded, and a guide wheel to guide the sleeve removal tool into the safety injection pipe, a horizontal movement carrier including bodies connected to each other by a link, a seating rod for seating of the sleeve removal tool, and moving wheels for movement of the horizontal movement carrier, and a vertical movement carrier including first and second anti-separation bars to prevent separation of the horizontal movement carrier.

Abstract: Disclosed is a method for removing a thermal sleeve from a cold leg of a reactor coolant system, which enables removal of an unintentionally separated thermal sleeve without implementation of a pipe cutting operation, preventing invasion of impurities into pipes and securing reliability in repetitious welding of the pipes. In particular, the method enables a remote operation and an underwater operation using wire ropes, thus being capable of minimizing a negative effect on workers due to radiation exposure.

Abstract: Disclosed is a device selection structure for selecting one or more devices, comprising: a plurality of devices each having an input port and an output port; and a device module including a movement plate installed movably in conjunction with the plurality of devices, an input connector, and an output connector, wherein the input and output ports of the plurality of devices and the input and output connectors of the device module are installed so that during movement of the movement plate, the input and output ports of the plurality of devices are sequentially connected, at predetermined positions, to the input and output connectors of the device module.

Abstract: A semiconductor integrated circuit device having a 6F2 layout is provided. The semiconductor integrated circuit device includes a substrate; a plurality of unit active regions disposed in the substrate and extending in a first direction; first and second access transistors including first and second gate lines disposed on the substrate and extending across the unit active regions in a second direction forming an acute angle with the first direction; a first junction area disposed in the substrate between the first and second gate lines and second junction areas disposed on sides of the first and second gate lines where the first junction area is not disposed; a plurality of bitlines disposed on the substrate and extending in a third direction forming an acute angle with the first direction; and a plurality of bitline contacts directly connecting the first junction area and the bitlines.

Abstract: Provided are a process monitoring apparatus and method. The process monitoring apparatus includes a process chamber in which a process is performed, a probe assembly disposed on the process chamber, and comprising a probe electrode, a plasma generator generating plasma around the probe assembly, and a drive processor applying an alternating current (AC) voltage having at least 2 fundamental frequencies to the probe assembly, and extracting process monitoring parameters.

Abstract: There are provided a steel for deep drawing, and a method for manufacturing the steel and a high pressure container. The steel for deep drawing includes, by weight: C: 0.25 to 0.40%, Si: 0.15 to 0.40%, Mn: 0.4 to 1.0%, Al: 0.001 to 0.05%, Cr: 0.8 to 1.2%, Mo: 0.15 to 0.8%, Ni: 1.0% or less, P: 0.015% or less, S: 0.015% or less, Ca: 0.0005 to 0.002%, Ti: 0.005 to 0.025%, B: 0.0005 to 0.0020% and the balance of Fe and inevitable impurities, wherein a microstructure of the steel has a triphase structure of ferrite, bainite and martensite. The steel for deep drawing may be useful to further improve the strength without the deterioration of the toughness by adding a trace of Ti and B, compared to the conventional steels having a strength of approximately 1100 MPa.

Abstract: Provided is a plasma diagnostic apparatus having a probe unit, which is inserted into a plasma or disposed at boundary of a plasma, the apparatus including: a signal supplying unit having a signal supplying source; a current detecting/voltage converting unit for applying a periodic voltage signal applied from the signal supplying unit to the probe unit, detecting the magnitude of the current flowing through the probe unit, and converting the detected current into a voltage; and a by-frequency measurement unit for computing the magnitude and phase of individual frequency components of the current flowing through the probe unit by receiving the voltage output from the current detecting/voltage converting unit as an input.

Abstract: Technologies related to forming metal lines of a semiconductor device are disclosed. A method of forming metal lines of a semiconductor device may include forming at least one interlayer insulating layer on a semiconductor substrate, forming via holes and trenches in the at least one interlayer insulating layer, forming an anti-diffusion film on the via holes and the trenches, depositing a seed Cu layer on the anti-diffusion film, after the seed Cu layer is deposited, depositing rhodium (Rh), and forming Cu line on the deposited Rh. The Rh improves an adhesive force between Cu layers and prevents oxide materials or a corrosion phenomenon from occurring on the seed Cu layer. Accordingly, occurrence of delamination in subsequent processes (for example, annealing and CMP) can be prevented or reduced.

Abstract: An enclosure device of a wireless communication apparatus, which has a tubular structure with increased heat dissipation not unknown heretofore. A section of the enclosure device has a polygonal or circular shape, such as a substantially cylindrical structure, and the enclosure, which has a plurality of radiation fins arranged on an outer surface of the enclosure in a vertical direction, is formed integrally with the radiation fins by using a compression method. Various communication devices of the wire communication apparatus are mounted on the interior of the enclosure. The structure is preferably formed by the radiation fins and exhibits an increased radiation effect than that of a structure where radiation fins are arranged side by side on a flat plane.

Abstract: Technologies related to forming metal lines of a semiconductor device are disclosed. A method of forming metal lines of a semiconductor device may include forming at least one interlayer insulating layer on a semiconductor substrate, forming via holes and trenches in the at least one interlayer insulating layer, forming an anti-diffusion film on the via holes and the trenches, depositing a seed Cu layer on the anti-diffusion film, after the seed Cu layer is deposited, depositing rhodium (Rh), and forming Cu line on the deposited Rh. The Rh improves an adhesive force between Cu layers and prevents oxide materials or a corrosion phenomenon from occurring on the seed Cu layer. Accordingly, occurrence of delamination in subsequent processes (for example, annealing and CMP) can be prevented or reduced.

Abstract: According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

Abstract: Provided are a substrate treating apparatus and a method of manufacturing the substrate treating apparatus. Processing units of a process equipment are modularized, and the modularized processing units are detachably disposed in a main frame. According to this characteristic, work time and work effort required for manufacturing the process equipment can be reduced. In addition, maintenance/repair of each of the processing units can be further easily performed.

Abstract: A system and method are disclosed, which controls congestion to efficiently transmit data through a network of grid node network in a grid computing environment where a large amount of data is processed.

Abstract: Provided is a plasma diagnostic apparatus includes a probe unit, which is inserted into a plasma or disposed at boundary of a plasma, the apparatus includes: a signal supplying unit having a signal supplying source; a current detecting/voltage converting unit for applying a periodic voltage signal applied from the signal supplying unit to the probe unit, detecting the magnitude of the current flowing through the probe unit, and converting the detected current into a voltage; and a by-frequency measurement unit for computing the magnitude and phase of individual frequency components of the current flowing through the probe unit by receiving the voltage output from the current detecting/voltage converting unit as an input.

Abstract: A semiconductor integrated circuit device having a 6F2 layout is provided. The semiconductor integrated circuit device includes a substrate; a plurality of unit active regions disposed in the substrate and extending in a first direction; first and second access transistors including first and second gate lines disposed on the substrate and extending across the unit active regions in a second direction forming an acute angle with the first direction; a first junction area disposed in the substrate between the first and second gate lines and second junction areas disposed on sides of the first and second gate lines where the first junction area is not disposed; a plurality of bitlines disposed on the substrate and extending in a third direction forming an acute angle with the first direction; and a plurality of bitline contacts directly connecting the first junction area and the bitlines.

Abstract: A semiconductor device employing a transistor having a recessed channel region and a method of fabricating the same is disclosed. A semiconductor substrate has an active region. A trench structure is defined within the active region. The trench structure includes an upper trench region adjacent to a surface of the active region, a lower trench region and a buffer trench region interposed between the upper trench region and the lower trench region. A width of the lower trench region may be greater than a width of the upper trench region. An inner wall of the trench structure may include a convex region interposed between the upper trench region and the buffer trench region and another convex region interposed between the buffer trench region and the lower trench region. A gate electrode is disposed in the trench structure. A gate dielectric layer is interposed between the gate electrode and the trench structure.

Abstract: A method of forming a metal line in a semiconductor device including forming an inter-metal dielectric (IMD) layer on the semiconductor substrate including the predetermined pattern, planarizing the IMD layer through a first CMP process, and patterning a via hole on the planarized substrate. The method further includes depositing a barrier metal layer in the via hole, filling a refractory metal in an upper part of the barrier metal layer, planarizing the substrate filled with the refractory metal by performing a second CMP process, forming a refractory metal oxide layer by oxidizing a residual refractory metal region created by the second CMP process, and forming a refractory metal plug by removing the refractory metal oxide layer through a third CMP process.

Abstract: According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

Abstract: A method of forming a metal line in a semiconductor device including forming an inter-metal dielectric (IMD) layer on the semiconductor substrate including the predetermined pattern, planarizing the IMD layer through a first CMP process, and patterning a via hole on the planarized substrate. The method further includes depositing a barrier metal layer in the via hole, filling a refractory metal in an upper part of the barrier metal layer, planarizing the substrate filled with the refractory metal by performing a second CMP process, forming a refractory metal oxide layer by oxidizing a residual refractory metal region created by the second CMP process, and forming a refractory metal plug by removing the refractory metal oxide layer through a third CMP process.

Abstract: A plasma display panel prevents error discharge from occurring between adjacent cells to display a clear color image on a screen. The plasma display panel includes a plurality of first sustain electrode lines successively formed on a substrate at a predetermined interval, a plurality of second sustain electrode lines coupled with each of the first sustain electrode lines one by one, a plurality of first discharge electrode pieces branched from each of the first sustain electrode lines, and a plurality of second discharge electrode pieces branched from each of the second sustain electrode lines, having discharge cells coupled with the first discharge electrode pieces.