Patents by Inventor Sung Hoan Be
Sung Hoan Be has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220133591Abstract: The present invention relates to a container, which accommodates a drug and is sealed, includes a container stopper part including at least one filling groove formed in order to inject a drug, and a container body including an opening into which the container stopper part is inserted and which is sealed, wherein the filling groove is formed in an outer wall surface of the container stopper part in a longitudinal direction in which the container stopper part is inserted thereinto and forms a passage which is formed between the outer wall surface of the container stopper part and an inner wall surface of the container body and through which the drug is injectable.Type: ApplicationFiled: March 8, 2020Publication date: May 5, 2022Inventors: Cheol Soo AHN, Sang Uk PARK, Sung Hoan CHO
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Patent number: 11244921Abstract: A semiconductor package is provided. The semiconductor package includes a connection structure, a semiconductor chip, and a connection metal. The connection structure includes a redistribution layer and a connection via layer. The semiconductor chip is disposed on the connection structure, and includes a connection pad. The connection metal is disposed on the connection structure and is electrically connected to the connection pad by the connection structure. The connection via layer includes a connection via having a major axis and a minor axis, and in a plan view, the minor axis of the connection via intersects with the connection metal.Type: GrantFiled: December 20, 2019Date of Patent: February 8, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang Eun Joo, Sung Hoan Kim, Kyung Moon Jung, Yong Hwan Kwon, Young Kyu Lim, Seong Hwan Park
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Patent number: 11171107Abstract: A semiconductor package includes: a semiconductor chip including a body having a first surface and a second surface, opposing the first surface, a connection pad disposed on the first surface of the body, and an extension pad disposed on the connection pad; and a connection structure including an insulating layer disposed on the first surface of the body of the semiconductor chip, a redistribution via penetrating through the insulating layer and having one side thereof in contact with the extension pad, and a redistribution layer disposed on the insulating layer and having a via pad in contact with the other side of the redistribution via, wherein a horizontal cross-sectional area of extension pad of the semiconductor chip is greater than a horizontal cross-sectional area of the connection pad of the semiconductor chip.Type: GrantFiled: December 13, 2019Date of Patent: November 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Gyu Jin Choi, Sung Hoan Kim, Chang Eun Joo, Chil Woo Kwon, Young Kyu Lim, Sung Uk Lee
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Publication number: 20200365545Abstract: A semiconductor package is provided. The semiconductor package includes a connection structure, a semiconductor chip, and a connection metal. The connection structure includes a redistribution layer and a connection via layer. The semiconductor chip is disposed on the connection structure, and includes a connection pad. The connection metal is disposed on the connection structure and is electrically connected to the connection pad by the connection structure. The connection via layer includes a connection via having a major axis and a minor axis, and in a plan view, the minor axis of the connection via intersects with the connection metal.Type: ApplicationFiled: December 20, 2019Publication date: November 19, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang Eun JOO, Sung Hoan KIM, Kyung Moon JUNG, Yong Hwan KWON, Young Kyu LIM, Seong Hwan PARK
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Publication number: 20200335468Abstract: A semiconductor package includes: a semiconductor chip including a body having a first surface and a second surface, opposing the first surface, a connection pad disposed on the first surface of the body, and an extension pad disposed on the connection pad; and a connection structure including an insulating layer disposed on the first surface of the body of the semiconductor chip, a redistribution via penetrating through the insulating layer and having one side thereof in contact with the extension pad, and a redistribution layer disposed on the insulating layer and having a via pad in contact with the other side of the redistribution via, wherein a horizontal cross-sectional area of extension pad of the semiconductor chip is greater than a horizontal cross-sectional area of the connection pad of the semiconductor chip.Type: ApplicationFiled: December 13, 2019Publication date: October 22, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Gyu Jin Choi, Sung Hoan Kim, Chang Eun Joo, Chil Woo Kwon, Young Kyu Lim, Sung Uk Lee
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Patent number: 10665549Abstract: A fan-out semiconductor package includes: a frame, including a wiring layer, and having a through-hole; a semiconductor chip disposed in the through-hole, and including a connection pad; an encapsulant covering at least a portion of each of the frame and an inactive surface of the semiconductor chip, and having a first opening exposing at least a portion of the wiring layer; an insulating layer disposed on the encapsulant, and having a second opening formed in the first opening to expose at least a portion of the wiring layer; a conductive pattern layer disposed on the insulating layer; a conductive via disposed in the second opening; and a connection structure disposed on the frame and an active surface of the semiconductor chip, and including one or more redistribution layers. The conductive pattern layer and the redistribution layer are electrically connected to the connection pad.Type: GrantFiled: February 6, 2019Date of Patent: May 26, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Hawn Bae, Jung Soo Kim, Won Choi, Sung Hoan Kim
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Publication number: 20200051918Abstract: A fan-out semiconductor package includes: a frame, including a wiring layer, and having a through-hole; a semiconductor chip disposed in the through-hole, and including a connection pad; an encapsulant covering at least a portion of each of the frame and an inactive surface of the semiconductor chip, and having a first opening exposing at least a portion of the wiring layer; an insulating layer disposed on the encapsulant, and having a second opening formed in the first opening to expose at least a portion of the wiring layer; a conductive pattern layer disposed on the insulating layer; a conductive via disposed in the second opening; and a connection structure disposed on the frame and an active surface of the semiconductor chip, and including one or more redistribution layers. The conductive pattern layer and the redistribution layer are electrically connected to the connection pad.Type: ApplicationFiled: February 6, 2019Publication date: February 13, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Hawn Bae, Jung Soo Kim, Won Choi, Sung Hoan Kim
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Publication number: 20120032269Abstract: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.Type: ApplicationFiled: October 13, 2011Publication date: February 9, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-ryul Chang, Tae-jung Lee, Sung-hoan Kim, Soo-cheol Lee
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Patent number: 8058185Abstract: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.Type: GrantFiled: October 23, 2007Date of Patent: November 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-ryul Chang, Tae-jung Lee, Sung-hoan Kim, Soo-cheol Lee
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Patent number: 7465978Abstract: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer protects the lightly doped source/drain regions. Accordingly, the protective oxide layer prevents the electric field from being concentrated to a bottom corner portion of the gate structure. In addition, the effective channel length is elongated since an electric power source is connected to heavily doped source/drain regions from an outside source of the transistor, instead of being connected to lightly doped source/drain regions.Type: GrantFiled: February 17, 2006Date of Patent: December 16, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Su Kim, Sung-Hoan Kim
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Publication number: 20080057689Abstract: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.Type: ApplicationFiled: October 23, 2007Publication date: March 6, 2008Inventors: Dong-ryul Chang, Tae-jung Lee, Sung-hoan Kim, Soo-cheol Lee
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Patent number: 7304387Abstract: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.Type: GrantFiled: May 5, 2006Date of Patent: December 4, 2007Assignee: Samsung Elecronics Co., Ltd.Inventors: Dong-ryul Chang, Tae-jung Lee, Sung-hoan Kim, Soo-cheol Lee
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Publication number: 20060278949Abstract: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.Type: ApplicationFiled: May 5, 2006Publication date: December 14, 2006Inventors: Dong-ryul Chang, Tae-jung Lee, Sung-hoan Kim, Soo-cheol Lee
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Publication number: 20060141726Abstract: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer protects the lightly doped source/drain regions. Accordingly, the protective oxide layer prevents the electric field from being concentrated to a bottom corner portion of the gate structure. In addition, the effective channel length is elongated since an electric power source is connected to heavily doped source/drain regions from an outside source of the transistor, instead of being connected to lightly doped source/drain regions.Type: ApplicationFiled: February 17, 2006Publication date: June 29, 2006Inventors: Ji-Su Kim, Sung-Hoan Kim
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Patent number: 7033896Abstract: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer protects the lightly doped source/drain regions. Accordingly, the protective oxide layer prevents the electric field from being concentrated to a bottom corner portion of the gate structure. In addition, the effective channel length is elongated since an electric power source is connected to heavily doped source/drain regions from an outside source of the transistor, instead of being connected to lightly doped source/drain regions.Type: GrantFiled: September 8, 2004Date of Patent: April 25, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Su Kim, Sung-Hoan Kim
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Patent number: 7029987Abstract: A method of manufacturing a semiconductor device having a shallow trench isolation includes steps of forming a mask layer on a semiconductor substrate, forming a shallow trench in a semiconductor substrate using the mask layer, forming at least one step in the semiconductor substrate at the top of the shallow trench, and then forming a liner layer over the entire surface of the semiconductor substrate so as to line the shallow trench and thereby offer protection during subsequent oxidation. When the mask layer is subsequently removed, the at least one step in the semiconductor substrate allows portions of the liner layer extending outside the shallow trench to be removed without creating problematic dents in the structure.Type: GrantFiled: March 27, 2002Date of Patent: April 18, 2006Assignee: Samsung Electronics Co., Ltd.Inventor: Sung-Hoan Kim
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Publication number: 20050062104Abstract: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer protects the lightly doped source/drain regions. Accordingly, the protective oxide layer prevents the electric field from being concentrated to a bottom corner portion of the gate structure. In addition, the effective channel length is elongated since an electric power source is connected to heavily doped source/drain regions from an outside source of the transistor, instead of being connected to lightly doped source/drain regions.Type: ApplicationFiled: September 8, 2004Publication date: March 24, 2005Inventors: Ji-Su Kim, Sung-Hoan Kim
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Patent number: 6827653Abstract: Disclosed herein is a wrist support for bowlers which prevents a user from being injured by shock applied to a user's wrist during bowling and which allows the user to accurately throw a bowling ball. The wrist support is designed to steplessly adjust horizontal and/or vertical angles between its hand back part, wrist part, and finger part, and is designed such that a fastening band unit is easily connected to and removed from a main body of the wrist part, and allows a user to feel comfortable when wearing the wrist support. The wrist support according to the present invention is designed such that click sounds are generated from the support when turning an adjusting knob provided at an angle adjusting part, thus allowing a user to confirm whether the angle adjusting part is operated or not, therefore providing reliability and convenience to a user.Type: GrantFiled: March 21, 2003Date of Patent: December 7, 2004Inventor: Sung-Hoan Be
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Publication number: 20040185950Abstract: Disclosed herein is a wrist support for bowlers which prevents a user from being injured by shock applied to a user's wrist during bowling and which allows the user to accurately throw a bowling ball. The wrist support is designed to steplessly adjust horizontal and/or vertical angles between its hand back part, wrist part, and finger part, and is designed such that a fastening band unit is easily connected to and removed from a main body of the wrist part, and allows a user to feel comfortable when wearing the wrist support. The wrist support according to the present invention is designed such that click sounds are generated from the support when turning an adjusting knob provided at an angle adjusting part, thus allowing a user to confirm whether the angle adjusting part is operated or not, therefore providing reliability and convenience to a user.Type: ApplicationFiled: March 21, 2003Publication date: September 23, 2004Inventor: Sung-Hoan Be
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Patent number: 6722671Abstract: A bag body for bowling bags. The bag body includes an elongated body member that is provided with a cavity and side open ends. Two lids are hinged to the body member at the side open ends of the body member to selectively open and close the side open ends, and provided with an exterior pouch. A partition is formed in the center portion of the cavity of the body member to divide the cavity into two sub-cavities. The partition may be pectinate and integrated with the body member into a single structure. The bag body may further comprise a cover made of synthetic resin of leather, the cover being provided with an auxiliary pouch and secured to the front portion of the body member by means of bars and bolts.Type: GrantFiled: February 20, 2001Date of Patent: April 20, 2004Inventor: Sung Hoan Be