Patents by Inventor Sung-Il Chang
Sung-Il Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11152390Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: GrantFiled: June 16, 2020Date of Patent: October 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
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Patent number: 11107833Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.Type: GrantFiled: April 28, 2020Date of Patent: August 31, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
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Publication number: 20200312878Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: ApplicationFiled: June 16, 2020Publication date: October 1, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-il CHANG, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
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Patent number: 10748929Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.Type: GrantFiled: January 10, 2020Date of Patent: August 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
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Publication number: 20200258908Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.Type: ApplicationFiled: April 28, 2020Publication date: August 13, 2020Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
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Patent number: 10700092Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: GrantFiled: June 14, 2019Date of Patent: June 30, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
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Publication number: 20200152659Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.Type: ApplicationFiled: January 10, 2020Publication date: May 14, 2020Inventors: CHANGHYUN LEE, CHANJIN PARK, BYOUNGKEUN SON, SUNG-IL CHANG
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Patent number: 10559590Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.Type: GrantFiled: June 28, 2018Date of Patent: February 11, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
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Publication number: 20190296047Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: ApplicationFiled: June 14, 2019Publication date: September 26, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-il CHANG, Jun-Hee LIM, Yong-Seok KIM, Tae-Young KIM, Jae-Sung SIM, Su-Jin AHN, Ji-Yeong HWANG
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Patent number: 10367002Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: GrantFiled: October 7, 2016Date of Patent: July 30, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
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Publication number: 20180323209Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.Type: ApplicationFiled: June 28, 2018Publication date: November 8, 2018Inventors: CHANGHYUN LEE, CHANJIN PARK, BYOUNGKEUN SON, SUNG-IL CHANG
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Patent number: 10038007Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.Type: GrantFiled: December 28, 2016Date of Patent: July 31, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
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Patent number: 9991275Abstract: A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern.Type: GrantFiled: March 1, 2016Date of Patent: June 5, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Il Chang, Changseok Kang, Byeong-In Choe
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Publication number: 20170110474Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.Type: ApplicationFiled: December 28, 2016Publication date: April 20, 2017Inventors: CHANGHYUN LEE, CHANJIN PARK, BYOUNGKEUN SON, SUNG-IL CHANG
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Publication number: 20170103998Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: ApplicationFiled: October 7, 2016Publication date: April 13, 2017Inventors: Sung-il Chang, Jun-Hee LIM, Yong-Seok KIM, Tae-Young KIM, Jae-Sung SIM, Su-Jin AHN, Ji-Yeong HWANG
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Patent number: 9536895Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.Type: GrantFiled: March 13, 2015Date of Patent: January 3, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
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Patent number: 9466704Abstract: A nonvolatile memory device and method of manufacturing the same are provided. In the nonvolatile memory device, a blocking insulation layer is provided between a trap insulation layer and a gate electrode. A fixed charge layer spaced apart from the gate electrode is provided in the blocking insulation layer. Accordingly, the reliability of the nonvolatile memory device is improved.Type: GrantFiled: May 30, 2014Date of Patent: October 11, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-il Chang, Changseok Kang, Jungdal Choi
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Patent number: 9385139Abstract: A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.Type: GrantFiled: June 29, 2015Date of Patent: July 5, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Il Chang, Youngwoo Park, Jaegoo Lee
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Publication number: 20160181274Abstract: A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern.Type: ApplicationFiled: March 1, 2016Publication date: June 23, 2016Inventors: SUNG-IL CHANG, CHANGSEOK KANG, BYEONG-IN CHOE
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Patent number: 9349879Abstract: A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.Type: GrantFiled: November 26, 2014Date of Patent: May 24, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Hyung Kim, Chang-Seok Kang, Sung-Il Chang, Jung-Dal Choi