Patents by Inventor Sung-Il Chang

Sung-Il Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200312878
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Application
    Filed: June 16, 2020
    Publication date: October 1, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-il CHANG, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
  • Patent number: 10748929
    Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
  • Publication number: 20200258908
    Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
    Type: Application
    Filed: April 28, 2020
    Publication date: August 13, 2020
    Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
  • Patent number: 10731755
    Abstract: A method of controlling driving of a CVT vehicle during cornering performed by a controller, may include determining whether it is necessary to perform an auxiliary control process to enhance a re-acceleration response after entering the corner, by determining a travelling state of the vehicle; setting a target gear ratio instead of a gear ratio obtained based on a shift pattern when the determining produces an affirmative result indicating that it is necessary to perform the auxiliary control process; and performing gear shifting of a CVT to follow the target gear ratio set in the setting of the gear ratio.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: August 4, 2020
    Assignees: Hyundai Motor Company, Kia Motors Corp.
    Inventors: Chan Hee Won, Sung Hwa Jeong, Woo Il Chang, Hyung Hee Lee, Jun Sung Park, Ho Young Kim
  • Patent number: 10700092
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: June 30, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
  • Publication number: 20200152659
    Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
    Type: Application
    Filed: January 10, 2020
    Publication date: May 14, 2020
    Inventors: CHANGHYUN LEE, CHANJIN PARK, BYOUNGKEUN SON, SUNG-IL CHANG
  • Publication number: 20200146273
    Abstract: An adhesive-type insect trap includes a body having a hole for insertion of an adhesive sheet; a light source mounting unit disposed on the body; and a cover which is detachably mounted on the body and has a through-hole in at least a part thereof, and an adhesive sheet including a sticky substance and a sheet. The body includes a guide unit by which the adhesive sheet is guided, and the cover comprises a light refraction unit therein or on a surface thereof.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 14, 2020
    Applicant: SEOUL VIOSYS CO., LTD.
    Inventors: Sang Hyun CHANG, Hoon Sik EOM, Si Ho YU, Gwang Ryong LEE, Chung Hoon LEE, Sung Il PARK
  • Patent number: 10649271
    Abstract: The present application relates to a polarizing plate and a display device. In the present application, a polarizing plate can be provided, which can be applied to a display device comprising a highly reflective panel to solve disadvantages while maintaining advantages of the device. In the present application, a display device comprising the polarizing plate and the highly reflective panel can also be provided.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: May 12, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Sung Hyun Nam, Kyung Ki Hong, Yeong Rae Chang, Heon Kim, Kyun Il Rah, Jong Hyun Jung, Byung Sun Lee, Eung Jin Jang, Jin Yong Park, Deok Woo Park, Ji Young Kim
  • Patent number: 10559590
    Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
  • Publication number: 20190357516
    Abstract: An adhesive-type insect trap includes a main body having an adhesive sheet insertion hole; a light source mounting unit disposed on the main body; a cover which is detachably mounted on the main body and has a through-hole in at least a part thereof; an adhesive sheet including a sticky substance and a sheet. The main body includes a guide unit by which the adhesive sheet is guided, and an adhesive sheet support unit for supporting the adhesive sheet.
    Type: Application
    Filed: January 5, 2018
    Publication date: November 28, 2019
    Applicant: SEOUL VIOSYS CO., LTD.
    Inventors: Sang Hyun CHANG, Hoon Sik EOM, Si Ho YU, Gwang Ryong LEE, Chung Hoon LEE, Sung Il PARK
  • Publication number: 20190350184
    Abstract: An adhesive-type insect trap includes a body having a hole for insertion of an adhesive sheet; a light source mounting unit disposed on the body; and a cover which is detachably mounted on the body and has a through-hole in at least a part thereof. The body further includes a light source seating unit provided so as to correspond to the light source mounting unit, and a light source may have one side thereof mounted on the light source mounting unit and the other side thereof seated on the light source seating unit.
    Type: Application
    Filed: January 8, 2018
    Publication date: November 21, 2019
    Applicant: SEOUL VIOSYS CO., LTD.
    Inventors: Sang Hyun CHANG, Hoon Sik EOM, Si Ho YU, Gwang Ryong LEE, Chung Hoon LEE, Sung Il PARK
  • Publication number: 20190296047
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Application
    Filed: June 14, 2019
    Publication date: September 26, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-il CHANG, Jun-Hee LIM, Yong-Seok KIM, Tae-Young KIM, Jae-Sung SIM, Su-Jin AHN, Ji-Yeong HWANG
  • Patent number: 10367002
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: July 30, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
  • Patent number: 10302833
    Abstract: The present application relates to a polarizer, a polarizing plate and a display device. The present application can provide a polarizer or a polarizing plate that is applied to various types of display devices, particularly to a display device having a highly reflective liquid crystal panel and that shows excellent characteristics. In addition, the present application can provide a display device including the polarizer or the polarizing plate.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: May 28, 2019
    Assignee: LG CHEM, LTD.
    Inventors: Sung Hyun Nam, Kyung Ki Hong, Eung Jin Jang, Yeong Rae Chang, Heon Kim, Kyun Il Rah, Jong Hyun Jung, Byung Sun Lee, Hong Jun Choi, Moon Soo Park, Sun Kug Kim
  • Publication number: 20180323209
    Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
    Type: Application
    Filed: June 28, 2018
    Publication date: November 8, 2018
    Inventors: CHANGHYUN LEE, CHANJIN PARK, BYOUNGKEUN SON, SUNG-IL CHANG
  • Patent number: 10038007
    Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: July 31, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
  • Patent number: 9991275
    Abstract: A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: June 5, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Il Chang, Changseok Kang, Byeong-In Choe
  • Publication number: 20170110474
    Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 20, 2017
    Inventors: CHANGHYUN LEE, CHANJIN PARK, BYOUNGKEUN SON, SUNG-IL CHANG
  • Publication number: 20170103998
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Application
    Filed: October 7, 2016
    Publication date: April 13, 2017
    Inventors: Sung-il Chang, Jun-Hee LIM, Yong-Seok KIM, Tae-Young KIM, Jae-Sung SIM, Su-Jin AHN, Ji-Yeong HWANG
  • Patent number: D854118
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: July 16, 2019
    Inventors: Sang Hyun Chang, Sung Il Park, Si Ho Yu, Chung Hoon Lee