Patents by Inventor Sung Jin Whang
Sung Jin Whang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9112044Abstract: A three-dimensional (3-D) non-volatile memory device includes a plurality of word line structures extended in parallel and including a plurality of interlayer dielectric layers and a plurality of word lines that are alternately stacked over a substrate, a plurality of channels protruding from the substrate configured to penetrate the plurality of interlayer dielectric layers and the plurality of word lines, and an air gap formed between the plurality of word line structures.Type: GrantFiled: December 8, 2011Date of Patent: August 18, 2015Assignee: SK Hynix Inc.Inventors: Sung Jin Whang, Ki Hong Lee
-
Publication number: 20150206591Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.Type: ApplicationFiled: March 30, 2015Publication date: July 23, 2015Inventors: Seiichi ARITOME, Hyun-Seung YOO, Sung-Jin WHANG
-
Patent number: 9019767Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.Type: GrantFiled: February 16, 2012Date of Patent: April 28, 2015Assignee: SK Hynix Inc.Inventors: Seiichi Aritome, Hyun-Seung Yoo, Sung-Jin Whang
-
Publication number: 20150099337Abstract: A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.Type: ApplicationFiled: December 16, 2014Publication date: April 9, 2015Inventors: Sung-Jin WHANG, Dong-Sun SHEEN, Seung-Ho PYI, Min-Soo KIM
-
Publication number: 20150099339Abstract: A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.Type: ApplicationFiled: December 12, 2014Publication date: April 9, 2015Inventors: Min-Soo KIM, Dong-Sun SHEEN, Seung-Ho PYI, Sung-Jin WHANG
-
Publication number: 20150079748Abstract: This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. In accordance with this technology, a lower part of the pipe connection gate electrode is buried in the substrate. Accordingly, electric resistance may be reduced because the pipe connection gate electrode may have an increased volume without a substantial increase of the height.Type: ApplicationFiled: November 21, 2014Publication date: March 19, 2015Inventors: Min-Soo KIM, Young-Jin LEE, Sung-Jin WHANG
-
Publication number: 20150072491Abstract: The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.Type: ApplicationFiled: November 13, 2014Publication date: March 12, 2015Inventors: Min Soo KIM, Dong Sun SHEEN, Young Jin LEE, Jin Hae CHOI, Joo Hee HAN, Sung Jin WHANG
-
Patent number: 8928063Abstract: A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.Type: GrantFiled: September 14, 2012Date of Patent: January 6, 2015Assignee: SK Hynix Inc.Inventors: Min-Soo Kim, Dong-Sun Sheen, Seung-Ho Pyi, Sung-Jin Whang
-
Patent number: 8928059Abstract: A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.Type: GrantFiled: September 6, 2012Date of Patent: January 6, 2015Assignee: SK Hynix Inc.Inventors: Sung-Jin Whang, Dong-Sun Sheen, Seung-Ho Pyi, Min-Soo Kim
-
Patent number: 8921922Abstract: This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. In accordance with this technology, a lower part of the pipe connection gate electrode is buried in the substrate. Accordingly, electric resistance may be reduced because the pipe connection gate electrode may have an increased volume without a substantial increase of the height.Type: GrantFiled: December 19, 2012Date of Patent: December 30, 2014Assignee: SK Hynix Inc.Inventors: Min-Soo Kim, Young-Jin Lee, Sung-Jin Whang
-
Publication number: 20140370702Abstract: A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.Type: ApplicationFiled: September 2, 2014Publication date: December 18, 2014Inventors: Sung-Jin WHANG, Moon-Sig JOO, Kwon HONG, Jung-Yeon LIM, Won-Kyu KIM, Bo-Min SEO, Kyoung-Eun CHANG
-
Patent number: 8860119Abstract: A nonvolatile memory device includes a substrate including a surface, a channel layer formed on the surface of the substrate, which protrudes perpendicularly from the surface, and a plurality of interlayer dielectric layers and a plurality of gate electrode layers alternately stacked along the channel layer, wherein the plurality of gate electrode layers protrude from the plurality of interlayer dielectric layers.Type: GrantFiled: September 5, 2012Date of Patent: October 14, 2014Assignee: SK Hynix Inc.Inventors: Min-Soo Kim, Dong-Sun Sheen, Seung-Ho Pyi, Sung-Jin Whang
-
Patent number: 8847300Abstract: A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.Type: GrantFiled: December 17, 2009Date of Patent: September 30, 2014Assignee: SK Hynix Inc.Inventors: Sung-Jin Whang, Moon-Sig Joo, Kwon Hong, Jung-Yeon Lim, Won-Kyu Kim, Bo-Min Seo, Kyoung-Eun Chang
-
Patent number: 8748966Abstract: A three dimensional non-volatile memory structure includes a plurality of interlayer dielectric layers and a plurality of control gates alternately stacked over a substrate, a channel formed to penetrate the plurality of interlayer dielectric layers and the plurality of control gates, a tunnel insulating layer formed to surround the channel, a plurality of floating gates disposed between the plurality of interlayer dielectric layers and the tunnel insulating layer, wherein the plurality of floating gates each have a thickness greater than a corresponding one of the interlayer dielectric layers, and a charge blocking layer disposed between the plurality of control gates and the plurality of floating gates.Type: GrantFiled: October 13, 2011Date of Patent: June 10, 2014Assignee: Hynix Semiconductor Inc.Inventors: Sung Jin Whang, Kwon Hong, Ki Hong Lee
-
Patent number: 8735962Abstract: A semiconductor device according to an embodiment of the present invention includes a vertical channel layer protruding upward from a semiconductor substrate, a tunnel insulating layer covering a sidewall of the vertical channel layer, a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween, a plurality of control gates enclosing the plurality of floating gates, respectively, and an interlayer insulating layer provided between the plurality of control gates.Type: GrantFiled: August 30, 2012Date of Patent: May 27, 2014Assignee: SK Hynix Inc.Inventors: Sung Jin Whang, Dong Sun Sheen, Seung Ho Pyi, Min Soo Kim
-
Patent number: 8711630Abstract: A programming method of a non-volatile memory device that includes a string of memory cells with a plurality of floating gates and a plurality of control gates disposed alternately, wherein each of the memory cells includes one floating gate and two control gates disposed adjacent to the floating gate and two neighboring memory cells share one control gate. The programming method includes applying a first program voltage to a first control gate of a selected memory cell and a second program voltage that is higher than the first program voltage to a second control gate of the selected memory cell, and applying a first pass voltage to a third control gate disposed adjacent to the first control gate and a second pass voltage that is lower than the first pass voltage to a fourth control gate disposed adjacent to the second control gate.Type: GrantFiled: December 22, 2011Date of Patent: April 29, 2014Assignee: Hynix Semiconductor Inc.Inventors: Seiichi Aritome, Hyun-Seung Yoo, Sung-Jin Whang
-
Publication number: 20140054672Abstract: This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a bottom buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled to the pipe channel layer and extended in a direction substantially perpendicular to the substrate, and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, wherein the pipe connection gate electrode includes a metal silicide layer formed within the groove. The electric resistance of the pipe connection gate electrode may be greatly reduced without an increase in a substantial height by forming the metal silicide layer buried in the substrate under the pipe connection gate electrode.Type: ApplicationFiled: December 18, 2012Publication date: February 27, 2014Applicant: SK HYNIX INC.Inventors: Min-Soo KIM, Young-Jin LEE, Jin-Hae CHOI, Joo-Hee HAN, Sung-Jin WHANG, Byung-Ho LEE
-
Publication number: 20140054674Abstract: This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. In accordance with this technology, a lower part of the pipe connection gate electrode is buried in the substrate. Accordingly, electric resistance may be reduced because the pipe connection gate electrode may have an increased volume without a substantial increase of the height.Type: ApplicationFiled: December 19, 2012Publication date: February 27, 2014Applicant: SK HYNIX INC.Inventors: Min-Soo KIM, Young-Jin LEE, Sung-Jin WHANG
-
Publication number: 20140054671Abstract: This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and etch stop layers including metal silicide and formed over the pipe connection gate electrode.Type: ApplicationFiled: December 18, 2012Publication date: February 27, 2014Applicant: SK hynix Inc.Inventors: Min-Soo KIM, Young-Jin LEE, Jin-Hae CHOI, Joo-Hee HAN, Sung-Jin WHANG, Byung-Ho LEE
-
Publication number: 20140054673Abstract: This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each connected with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and metal silicide layers configured to be in contact with the pipe connection gate electrode. The electric resistance of the pipe connection gate electrode may be greatly reduced without deteriorating the characteristics of the memory layers by forming the metal silicide layers coming in contact with the pipe connection gate electrode.Type: ApplicationFiled: December 19, 2012Publication date: February 27, 2014Applicant: SK HYNIX INC.Inventors: Min-Soo KIM, Young-Jin LEE, Sung-Jin WHANG