Abstract: The present invention relates to a novel amino-phenyl-sulfonyl-acetate derivative or a pharmaceutically acceptable salt thereof; and a pharmaceutical composition for preventing or treating diabetes comprising the same as an active ingredient.

Abstract: A hybrid clock data recovery circuit includes a linear phase detector configured to generate a recovered data signal by sampling an input data signal in response to a clock signal, and to generate up and down signals having a pulse width difference that is linearly proportional to a phase difference between the input data signal and the clock signal. An arbiter is configured to generate a bang-bang up signal representing that a phase of the input data signal leads a phase of the clock signal and a bang-bang down signal representing that the phase of the clock signal leads the phase of the input data signal based on the up and down signals. A digital loop filter is configured to generate a digital control code based on the bang-bang up and down signals. A digitally controlled oscillator is configured to generate an oscillating frequency of the clock signal in response to the digital control code, and to adjust the oscillating frequency of the clock signal in response to the up and down signals.

Abstract: An electronic device includes a communication circuit configured to communicate with an unmanned aerial vehicle (UAV) including a camera, a memory configured to store first flight information including a first flight pattern for a first location and first driving information of the camera, the first driving information corresponding to the first flight pattern, and a processor configured to be operatively connected with the communication circuit and the memory. The processor is configured to determine a flight reference location of the UAV, and control the UAV via the communication circuit such that the UAV flies based on the determined flight reference location and the first flight information.

Abstract: A hybrid clock data recovery circuit includes a linear phase detector configured to generate a recovered data signal by sampling an input data signal in response to a clock signal, and to generate up and down signals having a pulse width difference that is linearly proportional to a phase difference between the input data signal and the clock signal. An arbiter is configured to generate a bang-bang up signal representing that a phase of the input data signal leads a phase of the clock signal and a bang-bang down signal representing that the phase of the clock signal leads the phase of the input data signal based on the up and down signals. A digital loop filter is configured to generate a digital control code based on the bang-bang up and down signals. A digitally controlled oscillator is configured to generate an oscillating frequency of the clock signal in response to the digital control code, and to adjust the oscillating frequency of the clock signal in response to the up and down signals.

Abstract: A liquid crystal display device, including a display panel including data lines and gate lines intersecting the data lines, a gate driver configured to sequentially apply a scan signal to the gate lines, a data driver configured to apply data voltages corresponding to each gate lines to the data lines, a timing controller configured to control the gate driver and the data driver, a power source supply circuit configured to supply a positive power source and a negative power source, a common voltage feedback circuit configured to receive the positive power source and the negative power source from the power source supply circuit, receive a reference voltage and a common voltage from the display panel, and output an amplified feedback signal corresponding to a voltage level difference between the reference voltage and the common voltage.

Abstract: A display device includes a plurality of pixels, each including a first sub-pixel indicating a first color, a second sub-pixel indicating a second color, and a third sub-pixel indicating a third color, data lines coupled to pixels arranged in a first direction and configured to supply a data signal to the coupled pixels, gate lines coupled to pixels arranged in a second direction crossing the first direction and configured to supply a gate signal to the coupled pixels, and a compensation circuit configured to calculate a difference between grayscale values of a data signal to be supplied to the first to third sub-pixels, and generate a clock signal based on the difference that controls a start time at which the data signal is inputted to the pixels.

Abstract: An intake air control apparatus for a vehicle may include a valve flap provided in an air intake passage, the valve flap having a rotation shaft facing opposite sides of the air intake passage, to control a cross-sectional area of air intake flow according to a rotation angle thereof about the rotation shaft; a driving device supplying a driving force to the valve flap; and a port plate being provided in the air intake passage, with a longitudinal direction thereof being in parallel to a longitudinal direction of the air intake passage, the port plate dividing the air intake passage into an upper passage and a lower passage, wherein based on a width direction, at least a portion of the port plate has a height changing portion that changes a height of the port plate from a lower internal wall of the air intake passage.

Abstract: A display apparatus includes a display panel, a timing controller and a data driver. The display panel includes a data line and first and second pixels connected to the data line. The timing controller generates a data signal and a data kickback control signal in response to input image data. The data driver generates first and second data voltages in response to the data signal, generates a data kickback signal in response to the data kickback control signal, processes the data voltages and the data kickback signal, and outputs the first data voltage to the data line during a first duration, the second data voltage to the data line during a second duration, and a first kickback data voltage to the data line during a first data kickback duration. The first data kickback duration is between the first and second durations.

Abstract: A memory is provided, which comprises an electrically erasable and programmable read only memory (EEPROM) configured to store an operation system and to be rewritable in response to a write operation signal, an address comparator configured to be connected to Inter Integrated Circuit (I2C) lines and output the write operation signal to the EEPROM in response to an external signal, a digital-to-analog converter (DAC) unit configured to determine whether to connect a DAC resistor and the I2C lines in response to the external signal and a pull-up resistor unit configured to be connected to the I2C lines.

Abstract: A display panel driving apparatus includes a control circuit, a data driver and a gate driver. The control circuit is configured to receive a first control signal for recovering a clock signal from a display signal including image data and the clock signal, and calculate a root mean square of the first control signal to output a second control signal. The data driver is configured to receive the display signal, receive the second control signal, recover the clock signal from the display signal according to the second control signal, and output a data signal based on the image data to a data line of a display panel. The gate driving part is configured to output a gate signal to a gate line of the display panel.

Abstract: A multi-window control method and an electronic device supporting the same is provided. The multi-window control method includes changing a size of at least one specific window among a plurality of windows, and altering a focus to the at least one specific window based on a changed size of the at least one specific window.

Abstract: A multi-window control method and an electronic device supporting the same is provided. The multi-window control method includes changing a size of at least one specific window among a plurality of windows, and altering a focus to the at least one specific window based on a changed size of the at least one specific window.

Abstract: A method for controlling a combined display in an electronic device includes: performing connection to at least one sub-electronic device; receiving an image from the at least one sub-electronic device; and identifying relative position information of the at least one sub-electronic device with respect to the electronic device by using the image; and configuring the combined display in cooperation with the at least one sub-electronic device by using the relative position information.

Abstract: An anti-seismic apparatus for control element drive mechanisms of a nuclear reactor includes: an anti-seismic support plate including a plurality of insertion holes in which the control element drive mechanisms are respectively inserted; and bushings inserted between outer surfaces of the control element drive mechanisms and inner surfaces of the insertion holes. The support plate includes an upper support plate comprising a plurality of first insertion holes, a lower support plate comprising a plurality of second insertion holes at positions corresponding to the first insertion holes, and a connection part connecting the upper support plate and the lower support plate. The connection part includes a support beam vertically extending from an end portion of the lower support plate, an inner flange extending inward from an upper end portion of the support beam, and an outer flange extending outward from the upper end portion of the support beam.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A display apparatus includes: a display panel which displays an image; a data driver which supplies a data voltage to the display panel in response to a polarity control signal, where the polarity control signal controls a polarity of the data voltage; a timing controller which outputs a polarity signal corresponding to a polarity of the data voltage; and a polarity converter which receives a common voltage from a common electrode of the display panel and the polarity signal from the timing controller, where the polarity converter outputs the polarity control signal to the data driver in response to a difference in voltage level between the common voltage from the common electrode and the polarity signal from the timing controller.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A novel substituted N-(pyrrolidin-3-yl)-7H-pyrrolo[2,3-d]pyrimidin-4-amine and a use thereof as a Janus kinase (JAK) inhibitor are provided.

Abstract: A display device includes a display panel, a variable gate clock generator and a gate driver. The display panel includes a plurality of pixels coupled to a plurality of data lines and a plurality of gate lines, respectively. The variable gate clock generator generates a first variable gate clock signal and a second variable gate clock signal having respective duty ratios that are varied depending on a brightness of a frame image. The gate driver generates a plurality of gate driving signals for driving the gate lines in response to the first and second variable gate clock signals.

Abstract: The present invention relates to a novel amino-phenyl-sulfonyl-acetate derivative or a pharmaceutically acceptable salt thereof; and a pharmaceutical composition for preventing or treating diabetes comprising the same as an active ingredient.