Abstract: A thin film array panel is provided, which includes: a plurality of signal lines including contact parts for contact with an external device; a plurality of thin film transistors connected to the signal lines; an insulating layer formed on the signal lines and the thin film transistors; and a plurality of pixel electrodes formed on the insulating layer and connected to the thin film transistors, wherein the insulating layer includes a contact portion disposed on the contact parts of the signal lines and having a thickness smaller than other portions and the contact portion of the insulating layer includes an inclined portion having an inclination angle smaller than about 45 degrees.

Abstract: A thin film transistor substrate includes; a substrate, a plurality of gate lines disposed on the substrate, a plurality of data lines disposed substantially perpendicular to the gate lines, wherein the plurality of data liens include a plurality of outermost data lines, a plurality of thin film transistors (“TFTs”) connected to the gate and data lines, a plurality of pixel electrodes connected to the plurality of TFTs, and a plurality of dummy patterns connected to the outermost data lines.

Abstract: An apparatus and method for synchronizing a broadcast message in a broadband wireless communication system are provided.

Abstract: A calibration apparatus and method for supporting a Relay Station (RS) in a multiple antenna communication system are provided. The calibration method in the multiple antenna communication system which supports the RS includes, when a modem stage sends a downlink calibration signal, receiving, at a calibrator, the downlink calibration signal and estimating a downlink path channel, when the calibrator sends an uplink calibration signal, receiving, at the modem stage, the uplink calibration signal and estimating an uplink path channel, determining, at the modem stage, calibration coefficients per path not to generate a phase and amplitude difference with respect to the estimated uplink path channel and the estimated downlink path channel, and applying the calibration coefficients per path to corresponding antennas respectively.

Abstract: This invention relates to a non-sulfurous statuary material and a method of manufacturing the same, and particularly, to a novel statuary material containing no sulfur, which is capable of substituting for a conventional statuary material containing sulfur as a component of a statuary filling composition, in particular, an industrial statuary material, and to a method of manufacturing the same. In the case where the statuary material according to this invention is used, because it contains no sulfur, unlike conventional statuary material, environmental contamination and the generation of offensive odors due to sulfur are avoided, and furthermore, the use of material having a specific gravity lower than that of sulfur facilitates modeling.

Abstract: A display device according to an exemplary embodiment of the present invention includes: a plurality of pixels including switching elements; a plurality of pairs of first and second gate lines connected to the switching elements and separated from each other, transmitting a gate-on voltage for turning on the switching elements; and a plurality of data lines connected to the switching elements, transmitting data signals, wherein each pair of first and second gate lines is disposed between two adjacent pixel rows and is connected to one of the pixel rows.

Abstract: A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge, placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

Abstract: In an array substrate and a display apparatus, a pixel part has a plurality of gate lines, a plurality of data lines, and a plurality of pixels electrically connected to the gate and data lines. A driving circuit drives the pixel part electrically connected to a first end of the gate lines. An inspection circuit is electrically connected to a second end of the gate lines, and inspects the pixel part in response to an inspection signal externally provided. Thus, positions and causes for defects of the pixel part may be accurately detected, thereby improving inspecting efficiency.

Abstract: A substrate for a display panel includes a base substrate, a plurality of signal lines, a plurality of signal pads corresponding to first end portions of the signal lines, a shorting bar corresponding to second end portions of the signal lines, a plurality of bridge lines on the base substrate disposed between the signal line and the shorting bar which electrically connects the signal line and the shorting bar. A color filter array panel opposite a TFT LCD panel substrate includes a medium dam layer which fully overlaps the bridge lines of the TFT LCD panel substrate. A data TFT for inspection having a source electrode coupled to the signal line, a drain electrode coupled to any one of the shorting bars, and a gate electrode coupled to a data TFT driving signal line ensures the normal operation of the display panel after the array test.

Abstract: A liquid crystal display that is subject to pixel-high defects due to manufacturing anomalies is provided with programmable repair means for each pixel electrode. In one embodiment, a transistor-array substrate is provided with plural gate lines that are separated from each other by a first interval, plural data lines that are insulated from the gate lines while crossing the gate lines, and separated from each other by a second interval larger than the first interval, thereby defining plural pixel areas. Each pixel area has a corresponding pixel unit comprising a switching device, pixel electrode, and repair electrode. The repair electrode branches from a neighboring gate line and extends such that the repair electrode is in overlapping spaced-apart relation with the pixel electrode and selectively connectable to the pixel electrode.

Abstract: In an array substrate and a display apparatus, a pixel part has a plurality of gate lines, a plurality of data lines, and a plurality of pixels electrically connected to the gate and data lines. A driving circuit drives the pixel part electrically connected to a first end of the gate lines. An inspection circuit is electrically connected to a second end of the gate lines, and inspects the pixel part in response to an inspection signal externally provided. Thus, positions and causes for defects of the pixel part may be accurately detected, thereby improving inspecting efficiency.

Abstract: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

Abstract: Disclosed is a liquid crystal display device including a first substrate, a second substrate, and a liquid crystal layer interposed there between. The first substrate is provided with gate lines and data lines thereon. The gate lines and data lines cross with each other and are insulated from each other. Pixel electrodes are stacked on the gate lines and data lines. Each pixel electrode includes first and second sub-pixel electrodes spaced apart from each other and a connection electrode, which connects the first sub-pixel electrode to the second sub-pixel electrode. The second substrate is provided with a common electrode thereon. The common electrode includes a first domain divider formed on the center of the first sub-pixel electrode and a second domain divider formed on the center of the second sub-pixel electrode.

Abstract: In accordance with one or more embodiments of the present invention, a driving portion of a display device is formed on the same plane as a display portion of a display device. The driving portion includes cumulative layers of a control electrode, a first insulating layer, a semiconductor layer, a second insulating layer, an input electrode, an output electrode, and an auxiliary layer on top of the layers. Thus, the transistors within the driving portion may be more compact, while possibly reducing the likelihood of a short circuit between the electrodes.

Abstract: A gate driving circuit includes cascaded stages, each including a pull-up part, a carry part, a pull-up driving part, a holding part and an inverter. The pull-up part pulls up a gate voltage to an input clock. The carry part pulls up a carry voltage to the input clock. The pull-up driving part is connected to a control terminal (Q-node) common to the carry part and the pull-up part, and receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part. The holding part holds the gate voltage at an off-voltage, and the inverter controls at least one of turning on the holding part and turning off the holding part based on an inverter clock. A high level of the inverter clock in a given horizontal period (1H) temporally precedes a high level of the input clock by a predetermined time interval.

Abstract: An apparatus and method for creating a data path for a broadcasting service in a cellular network is provided. In a method for creating a data path to provide a broadcasting service in a cellular network, a broadcast server transmits a session start request message to an Access Service Network-GateWay (ASN_GW) before transmission of Multicast and Broadcast Service (MBS) data, to request a multicast connection setup. The ASN_GW establishes a multicast connection between the broadcast server and the ASN_GW on the basis of information of the session start request message. The ASN_GW transmits a session start response message to the broadcast server in response to the session start request message, after establishment of the multicast connection between the broadcast server and the ASN_GW. The ASN_GW transmits a path registration request message to at least one base station associated with a broadcast zone, to request MBS data path establishment and air resource reservation.

Abstract: A gate driving circuit includes stages, the stages being cascaded and each including: a pull-up part which pulls up a gate voltage to a clock signal during a horizontal scanning period (1H); a carry part which pulls up a carry voltage to the clock signal during the horizontal scanning period (1H); a pull-up driving part connected to a control terminal (Q-node) common to the carry part and the pull-up part and which receives a previous carry voltage from a first previous stage to turn on the pull-up part and the carry part; and a ripple preventing part which prevents a ripple generated at a previous Q-node of a second previous stage based on a ripple generated at the Q-node of the carry part and the pull-up part.

Abstract: A display substrate includes a first switching element, a second switching element, a first pixel electrode, a second pixel electrode, a main storage electrode and a sub-storage electrode. The first switching element is connected to a data line and a first gate line. The second switching element is connected to the data line and a second gate line adjacent to the first gate line. The first pixel electrode is electrically connected to the first switching element. The second pixel electrode is electrically connected to the second switching element. The main storage electrode is disposed in an area between the first pixel electrode and the second electrode to overlap with first ends of the first and second pixel electrodes. The sub-storage electrode is spaced apart from the first and second gate lines.

Abstract: Disclosed is a liquid crystal display device including a first substrate, a second substrate, and a liquid crystal layer interposed there between. The first substrate is provided with gate lines and data lines thereon. The gate lines and data lines cross with each other and are insulated from each other. Pixel electrodes are stacked on the gate lines and data lines. Each pixel electrode includes first and second sub-pixel electrodes spaced apart from each other and a connection electrode, which connects the first sub-pixel electrode to the second sub-pixel electrode. The second substrate is provided with a common electrode thereon. The common electrode includes a first domain divider formed on the center of the first sub-pixel electrode and a second domain divider formed on the center of the second sub-pixel electrode.

Abstract: Disclosed is a thin film transistor array panel. The panel includes a plurality of pixels arranged in the form of a matrix each with a pixel electrode and a switching element connected to the pixel electrode, and a plurality of gate lines connected to the switching elements and extending in the row direction. A pair of the gate lines are connected to pixels in each pixel row. A plurality of data lines are connected to the switching elements, and elongated in the column direction. Each data line is provided between two columns of the pixels. The respective data lines are horizontally bent between the two adjacent gate lines, and vertically extend between the two pixel rows.