Abstract: A liquid crystal display (“LCD”) device includes a display panel, a data driving part, and at least one first light-blocking part and at least one second light-blocking part. The display panel includes a plurality of pixels and a plurality of data lines. The pixels are arranged in a column direction and a row direction. At least one of the data lines extends in a zigzag shape along the column direction to be discontinuously disposed between two adjacent columns of the pixels. The at least one data line is electrically connected to two of the pixels that are adjacent in the row direction. The second light-blocking part is thinner than the first light-blocking part. The first light-blocking part and the second light-blocking are repeatedly disposed on an area between two adjacent columns of the pixels. The data driving part applies a data signal to the data lines.

Abstract: A thin film transistor (“TFT”) display plate, capable of reducing a load on a gate line, increasing an aperture ratio and preventing light leakage, includes an insulating substrate, a gate line formed on the insulating substrate, a storage electrode line spaced apart from the gate line and formed on an insulating substrate, a data line insulated from the gate line and the storage electrode line and intersecting the gate line, a pixel electrode formed for each pixel defined by the gate line and the data line, a thin film transistor (“TFT”) connected to the gate line and the data line to apply a voltage to the pixel electrode, and a storage electrode formed on the same layer as the data line and connected to the storage electrode line to form one terminal of a storage capacitor along with the pixel electrode as the other terminal of the storage capacitor.

Abstract: A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

Abstract: A gate driving circuit includes stages connected in series. In a stage, a pull-up part pulls up a present gate signal to a level of a first clock signal, and a pull-down part receives a next gate signal from a next stage to discharge the present gate signal to an off-voltage. A pull-up driving part turns on or turns off the pull-up part and the carry part. A holding part holds the present gate signal at the off-voltage and a present inverter turns on or turns off the holding part in response to the first clock signal. A ripple preventing capacitor is connected between a present node and an output terminal of a previous stage's inverter to prevent a ripple at the present Q-node in response to an output signal from the previous inverter.

Abstract: An array substrate (100a) includes a transparent substrate (304), a first insulation layer (306) and a pixel electrode (103). The transparent substrate (304) includes a display region (DR) that displays an image, a peripheral region (PR) having a driving circuit (101) for displaying an image through the display region, and a sealine region (SLR) that surrounds the display region (DR) to define the display region and the peripheral region (PR). The first insulation layer (306) is formed over the transparent substrate (304), and the first insulation layer (306) has an opening window (301) in the sealine region (SLR). The pixel electrode (103) is formed on the first insulation layer (306) of the display region (DR). The bonding between a color filter substrate (401) and an array substrate (100a) is improved. Furthermore, liquid crystal material is completely filled into between the color filter substrate and the array substrate.

Abstract: A display substrate includes a first metal pattern formed on a substrate and includes a data line to which a pixel voltage is applied, an insulating layer formed on the substrate on which the first metal pattern is formed, an active pattern formed on the insulating layer, a second metal pattern formed on the insulating layer and including a gate line and a storage line, the gate line crossing the data line, a scanning signal applied to the gate line, a protective layer formed on the substrate on which the second metal pattern is formed, and a pixel electrode formed on the protective layer. A method for manufacturing the display substrate, and a display apparatus including the display substrate are further provided.

Abstract: A thin film array panel is provided, which includes: a plurality of signal lines including contact parts for contact with an external device; a plurality of thin film transistors connected to the signal lines; an insulating layer formed on the signal lines and the thin film transistors; and a plurality of pixel electrodes formed on the insulating layer and connected to the thin film transistors, wherein the insulating layer includes a contact portion disposed on the contact parts of the signal lines and having a thickness smaller than other portions and the contact portion of the insulating layer includes an inclined portion having an inclination angle smaller than about 45 degrees.

Abstract: The present invention provides a liquid crystal display (“LCD”), a method of manufacturing the same, and a method of repairing the same capable of obtaining a wide viewing angle and improving a success ratio of repair. The LCD includes a gate line, a first data line intersecting the gate line, a thin film transistor (“TFT”) connected with the gate line and the first data line, a pixel electrode connected with the TFT, a first conductive pattern partially overlapping with a first end of the pixel electrode, a second conductive pattern partially overlapping with a second end of the pixel electrode, and a storage capacitor, wherein at least one of the first conductive pattern and the second conductive pattern partially overlaps with the first data line adjacent to the first end of the pixel electrode and a second data line adjacent to the second end of the pixel electrode, respectively.

Abstract: A display substrate includes a substrate, a first insulating layer, an undercut compensating member, a first electrode, a second insulating layer and a first conductive pattern. The first insulating layer is formed on the substrate. The undercut compensating member is formed on the first insulating layer. The undercut compensating member has an etching rate smaller than that of the first insulating layer. The first electrode is formed on a portion of the undercut compensating member. The second insulating layer is formed on the first insulating layer. The second insulating layer has a contact hole through which a portion of the first electrode and a remaining portion of the undercut compensating member. The first conductive pattern electrically connected to the first electrode through the contact hole.

Abstract: In an array substrate and a display apparatus, a gate line receives a gate pulse during a present 1H period and a data line receives a pixel voltage having a polarity inverted at every frame. When a thin film transistor is turned on in response to the gate pulse during the present 1H period, a pixel electrode receives the pixel voltage through the thin film transistor during the present 1H period. A pre-charging part pre-charges the pixel electrode to a common voltage that is a reference voltage of the pixel voltage in response to a previous gate pulse during a previous 1H period.

Abstract: The present invention relates to a module and method for detecting a defect of a thin film transistor (TFT) substrate, which can detect disconnection of a gate line of the TFT substrate having gate drivers provided with a dual structure in which the gate drivers are provided at both sides of the gate lines. There is provided a module and method for detecting a defect of a TFT substrate, wherein gate lines are separated into two portions by cutting a central region of the gate lines, gate power is supplied to the gate lines of which central portions are cut through gate drivers provided at both sides of the gate lines, and a signal of a negative voltage level is supplied to data lines, so that disconnection of the gate lines can be detected.

Abstract: A liquid crystal display device comprises at least two insulating layers formed on a first conductive layer, a second conductive layer formed between the at least two insulating layers, a first contact hole penetrating an upper insulating layer of the at least two insulating layers on the second conductive layer, a second contact hole penetrating the at least two insulating layers and exposing a portion of the first conductive layer, and a contact part comprising a bridge electrode formed of a third conductive layer for connecting the first and second conductive layers through the first and second contact holes. The second contact hole comprises an internal hole penetrating the at least two insulating layers and an external hole surrounding the internal hole forming in the upper insulating layers.

Abstract: A display panel includes; a lower substrate including a display area which includes a pixel and a peripheral area surrounding the display area, the peripheral area including a first peripheral area, a second peripheral area, a third peripheral area and a fourth peripheral area, the lower substrate including; a signal line electrically connected to the pixel, an electrostatic control pattern disposed in the first peripheral area and which provides an electrostatic dissipation path, and a repair line disposed between the display area and the electrostatic control pattern and which is vertically aligned with the signal line, an upper substrate facing the lower substrate and a liquid crystal layer disposed between the lower substrate and the upper substrate.

Abstract: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

Abstract: A display panel and a method of manufacturing the same are provided, which can prevent the deterioration of input sensitivity to the panel, and maximize the aperture ratio of the panel. The display panel includes a first substrate, a gate line and a data line crossing each other on the first substrate, in a manner that the gate line and the data line are electrically insulated from each other. The display panel further comprises a first sensor wire formed in parallel to the data line, a second sensor wire formed to overlap the data line in parallel to the data line, a second substrate arranged opposite to the first substrate, and a sensor spacer formed on the second substrate to project toward the first substrate.

Abstract: A base station is capable of performing 4-beamforming using Radio Units (RU), each having two paths in a wireless communication system. The base station includes a Digital Unit (DU), a first RU, and a second RU. The DU performs a mutual conversion function between an information bit line and a digital signal, calculates beamforming coefficients for 4-beamforming, and performs the 4-beamforming using the beamforming coefficients. The first RU has two Radio Frequency (RF) paths, extracts a clock signal from a digital signal from the DU, and provides the clock signal to the second RU. The second RU has two RF paths and operates according to the clock signal provided from the first RU.

Abstract: A thin film array panel is provided, which includes: a plurality of signal lines including contact parts for contact with an external device; a plurality of thin film transistors connected to the signal lines; an insulating layer formed on the signal lines and the thin film transistors; and a plurality of pixel electrodes formed on the insulating layer and connected to the thin film transistors, wherein the insulating layer includes a contact portion disposed on the contact parts of the signal lines and having a thickness smaller than other portions and the contact portion of the insulating layer includes an inclined portion having an inclination angle smaller than about 45 degrees.

Abstract: A display apparatus includes: a plurality of pixel blocks, each pixel block of the plurality of pixel blocks including a first pixel electrode connected to a first switching element and a second pixel electrode connected to a second switching element; gate lines which extend along a first direction and include a first gate line connected to the first switching element and a second gate line connected to the second switching element; and data lines which extend along a second direction intersecting the first direction. A gate voltage is applied to the first gate line before the second gate line, and the first pixel electrode of each of the pixel blocks displays a same color.

Abstract: A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal.

Abstract: Provided are a display panel which can detect a touch position derived from a user's touch and can prevent erroneous touch position data from being generated even when an erroneous connection to a position sensing line is present due a processing deviation or a cell gap deviation, and a manufacturing method of the same.