Abstract: A semiconductor chip structure may include a semiconductor chip, a first insulation layer and a redistribution layer. The first insulation layer may be formed on the semiconductor chip. The first insulation layer may have at least one first groove formed at an upper surface portion of the first insulation layer. Further, the at least one first groove may have an upper width and a lower width greater than the upper width. The redistribution layer may be partially formed on the first insulation layer. The redistribution layer may have at least one first protrusion formed on a lower surface portion of the redistribution layer. The first protrusion may have an upper width and a lower width less than the upper width. The first protrusion may be inserted into the at least one first groove.

Abstract: Example embodiments may include an oligomer probe array chip based on an analysis-friendly layout. Example oligomer probe array chips may include a substrate, a main array on the substrate having a plurality of sub-arrays in rows or panels, and/or a plurality of alignment spot arrays outside of each of the sub-arrays. The sub-arrays may include a plurality of spots arranged in a matrix to which oligomer probes having different sequences may be attached. Example embodiments may further provide masks for fabricating oligomer probe array chips and hybridization analysis methods of oligomer probe array chips.

Abstract: A multi-bridge-channel MOSFET (MBCFET) may be formed by forming a stacked structure on a substrate that includes channel layers and interchannel layers interposed between the channel layers. Trenches are formed by selectively etching the stacked structure. The trenches run across the stacked structure parallel to each other and separate a first stacked portion including channel patterns and interchannel patterns from second stacked portions including channel and interchannel layers remaining on both sides of the first stacked portion. First source and drain regions are grown using selective epitaxial growth. The first source and drain regions fill the trenches and connect to second source and drain regions defined by the second stacked portions. Marginal sections of the interchannel patterns of the first stacked portion are selectively exposed. Through tunnels are formed by selectively removing the interchannel patterns of the first stacked portion beginning with the exposed marginal sections.

Abstract: A data output circuit includes a sense amplifier and first and second latches. The sense amplifier is for amplifying differential data to generate amplified differential data. The first latch is for latching the amplified differential data to generate first latched data having a same phase as the amplified differential data. The second latch is for latching the amplified differential data to generate second latched data having an opposite phase from the amplified differential data. The amplified differential data from outputs of the sense amplifier are applied substantially simultaneously to inputs of the first and second latches.

Abstract: Provided is a high power semiconductor package including: an insulation substrate having first and second surfaces opposite to each other; an interconnection patterns formed on the first surface of the insulation substrate, the interconnection patterns including a plurality of first dimples; a power control semiconductor chip mounted on the first surface of the insulation substrate, the power control semiconductor chip electrically connected with the interconnection patterns; and an encapsulation member encapsulating the insulation substrate, the interconnection patterns, and the power control semiconductor chip and exposing at least a portion of the second surface of the insulation substrate.

Abstract: The present invention provides a biochip kit including a first housing; a biochip disposed inside the first housing and configured to include a plurality of molecular probes; and a second housing joined to the first housing and configured to form a reaction space with the first housing and to cover the biochip, wherein the second housing and the first housing are removably joined in a configuration to allow exposure of an upper surface of the biochip. Methods of testing biological samples using the biochip kits are also provided.

Abstract: A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.

Abstract: A stack package includes an upper semiconductor chip having a plurality of first bonding pads which are formed on an upper surface of the upper semiconductor chip and via-holes which are defined in the upper semiconductor chip under the respective first bonding pads; and a lower semiconductor chip attached to a lower surface of the upper semiconductor chip and having a plurality of second bonding pads which are formed on an upper surface of the lower semiconductor chip and bumps which are formed on the respective second bonding pads and are inserted into the respective via-holes to be come into the respective first bonding pads.

Abstract: A thin film transistor substrate and a liquid crystal display capable of eliminating residual images and enhancing clarity are presented. The thin film transistor substrate includes a charge-up capacitor for increasing electric charge in a first pixel electrode of a first pixel capacitor and a charge-down capacitor decreasing electric charge in a second pixel electrode of a second pixel capacitor. An extension electrode portion of the charge-up capacitor is formed in the shape of a frame to reduce any variation in the overlapping area between the first pixel electrode and the extension electrode portion caused by an alignment error generated during the manufacturing process.

Abstract: An apparatus and method for selecting a broadcast channel are provided. The apparatus includes a controller which constructs a broadcast information providing screen image such that broadcast information of each of a plurality of channels is arranged at a location corresponding to a location of each of a plurality of user input keys, based on arrangement information of at least one piece of the user input keys; a display processor which controls outputting of the broadcast information providing screen image; and a user input signal receiving unit which receives an input signal from one of the user input keys, wherein the controller selects a broadcast channel corresponding to broadcast information at a location corresponding to a location of the user input key through which the input signal is received.

Abstract: Embodiments of the invention include a partially insulated field effect transistor and a method of fabricating the same. According to some embodiments, a semiconductor substrate is formed by sequentially stacking a bottom semiconductor layer, a sacrificial layer, and a top semiconductor layer. The sacrificial layer may be removed to form a buried gap region between the bottom semiconductor layer and the top semiconductor layer. Then, a transistor may be formed on the semiconductor substrate. The sacrificial layer may be a crystalline semiconductor formed by an epitaxial growth technology.

Abstract: Provided is a method and apparatus for managing the power of a portable computer system, in which a convenient user interface is provided. The method includes calculating a range of a desired time-of-use based on power consumption of the portable computer system and a remaining battery capacity at a minimum power level of the portable computer system, providing the calculated range of the desired time-of-use and a desired time input box that allows a user to input the desired time-of-use, inputting the desired time-of-use through the desired time input box, and resetting the power level of the portable computer system according to the input desired time-of-use.

Abstract: A correction method and a system thereof automatically perform a measurement and an analysis for a photomask critical dimension (CD), to satisfy a desired CD uniformity and a desired mean-to-target (MTT) data. A correction for a portion where a CD error has occurred may be performed.

Abstract: There is provided a back light unit having a light guide buffer plate. The back light unit having a light guide buffer plate includes a light source for generating the light when a power source is applied; a light guide panel whose light-receiving vertical surface that the light emitted from the light source enters is provided with a first prism pattern and whose bottom surface is provided with a refraction pattern, thereby converting the incident light from the light-receiving vertical surface into a surface light source; a reflection unit disposed in a bottom surface of the light guide panel to reflect light toward the light guide panel; and a buffer disposed between the light source and the light guide panel and whose light-emitting vertical surface corresponding to the light-receiving vertical surface of the light guide panel is provided with a second prism pattern.

Abstract: Provided are a phase-change memory device and a method of fabricating the same. The phase-change memory device includes a transistor disposed on a semiconductor substrate and including a gate electrode and first and second impurity regions disposed on both sides of the gate electrode; a bit line electrically connected to the first impurity region; and a phase-change resistor electrically connected to the second impurity region, wherein the phase-change resistor includes: a lower electrode formed of a doped SiGe layer; a phase-change layer contacting the lower electrode; and an upper electrode connected to the phase-change layer. The lower electrode is formed of the doped SiGe layer, which has a high resistivity and a low thermal conductivity, thereby reducing a reset current and the power consumption of the entire phase-change memory device.

Abstract: An electric stimulator for alpha-wave derivation is characterized in that frequency selected from a range of 1 Hz to 50 Hz, preferably, 7 Hz to 14 Hz, and an output voltage are applied to auricle of a patient's ears to derive alpha-waves, and that cycle and intensity of stimulation are varied depending upon body temperature and blood sugar. Prompt reaction may be obtained by directly applying the voltage to the ears, and the reaction may continue when stimulation is extended. In addition, it is suitable to treat various diseases having common cause due to stress or arousal reaction in the human body.

Abstract: A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel region between the first and second charge storage layers, and a gate electrode on the insulating layer opposite the channel region and between inner sidewalls of the first and second charge storage layers. The gate electrode extends away from the substrate beyond the first and second charge storage layers. The device further includes second and third insulating layers extending from adjacent the inner sidewalls of the first and second charge storage layers along portions of the gate electrode beyond the first and second charge storage layers. Related methods of fabrication are also discussed.

Abstract: Disclosed is a method for preparation of a liquid crystal film having uniaxial alignment, comprising steps of: elevating temperature of a substrate coated with a nanostructure formed of liquid crystal molecules to a value sufficient to alter the nanostructure into a liquid phase; and decreasing the temperature to another value sufficient to again alter the liquid phase into a liquid crystal phase in the presence of a magnetic field to horizontally align the nanostructure of liquid crystal molecules.

Abstract: Provided are a 3-port orthogonal mode transducer, and a receiver and receiving method using the same. The 3-port orthogonal mode transducer includes: a transmission port having a rectangular shape elongated in a horizontal direction and configured to transmit a Ka-band (30 GHz) vertical polarization signal; a first reception port having a rectangular shape inclined at about +45 degrees at a location being at about +45 degrees with respect to the transmission port and configured to receive a K-band (20 GHz) vertical or horizontal polarization signal phased-delayed about +45 degrees; and a second reception port having a rectangular shape inclined at about ?45 degrees at a location being at about ?45 degrees with respect to the transmission port and configured to receive a K-band (20 GHz) vertical or horizontal polarization signal phase-delayed about ?45 degrees.