Abstract: Provided is a phase-change element capable of operating with low power consumptions and a method of manufacturing the same. The phase-change element comprises a first electrode used as a heating layer, a second electrode, which is disposed opposite to the first electrode, and a memory layer made of a phase-change material located contacts the side surfaces of the first electrode and the second electrode.

Abstract: Disclosed herein is a tape feeder for chip mounters. The tape feeder is constructed so that front and rear locators are restrained by a restraint slot of a cam slider moving horizontally, and bearings of the front and rear locators alternatively execute vertical and horizontal movements while sliding along the restraint slot by a reciprocating motion of a cam slider, thus repeatedly moving a carrier tape backward while locking the carrier tape and moving the carrier tape forward while releasing the carrier tape, therefore allowing the carrier tape to be fed precisely. The tape feeder allows the carrier tape to be fed precisely, and prevents chips from being turned over and removed from the carrier tape when a vinyl cover is discharged, thus minimizing a malfunction of the chip mounter during an operation of the chips and thereby maximizing operational reliability. Further, the tape feeder allows the number of elements to be reduced, in addition to achieving a slim construction.

Abstract: Provided is a method for fabricating an organic semiconductor transistor having an organic polymeric gate insulating layer. The method includes forming an organic gate insulating layer on a substrate by a vapor deposition method using organic monomer sources, and causing a polymerization reaction to occur in the organic gate insulating layer to complete an organic polymeric gate insulating layer. Since the vapor deposition method, which is a low-temperature dry-type technique, is employed, the organic polymeric gate insulating layer can be uniformly formed on a large-area substrate by a simplified in-situ process.

Abstract: Bit line sense amplifier driving control circuits and methods for synchronous DRAMs selectively supply and suspend supply of operating voltages for bit line sense amplifiers. More specifically, a synchronous DRAM includes a memory cell array including at least a first column block and a second column block that are divided according to column address, first bit line sense amplifiers that are configured to sense data that is output from the first column block of the memory cell array, and second bit line sense amplifiers that are configured to sense data that is output from the second column block of the memory cell array. A bit line sense amplifier driving control circuit or method is responsive to a row address select signal, to supply an operating voltage to the first and second bit line sense amplifiers, and is responsive to a column select signal that selects a column address in the first column block, to suspend supplying an operating voltage to the second bit line sense amplifiers.

Abstract: A protein conjugate having a prolonged in vivo half-life of a physiological activity, comprising i) a physiologically active polypeptide, ii) a non-peptidic polymer, and iii) an immunoglobulin, is useful for the development of a polypeptide drug due to the enhanced in vivo stability and prolonged half-life in blood, while reducing the possibility of inducing an immune response.

Abstract: A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) semiconductor device is provided that prevents a conflict between data read from and data written to the DDR SDRAM semiconductor device when data is written to the DDR SDRAM semiconductor device, which includes a delay locked loop (“DLL”) circuit, a clock signal control unit, an output unit, and an output control unit, where the DLL circuit compensates for skew of an input clock signal and generates an output clock signal; the clock signal control unit receives a read signal activated when data stored in the DDR SDRAM semiconductor device is read out, a DLL locking signal activated when the DLL circuit performs a locking operation on the input clock signal, and the output clock signal, and outputs the output clock signal when either the read signal or the DLL locking signal is active; the output unit buffers data stored in the DDR SDRAM semiconductor device and outputs the data to outside of the D

Abstract: A signal line driving circuit includes an inversion buffer, a pulse generator, a first signal buffer, and a second signal buffer. Here, the inversion buffer receives an input signal and includes an output terminal connected to the signal line to drive the signal line. The pulse generator receives the input signal to generate a pulse signal. The first signal buffer has a control terminal connected to an output terminal of the pulse generator and an input/output terminal connected to a node of the signal line. The first signal buffer reduces the rising transition time of a signal propagating on the signal line in response to a first control signal. The second signal buffer has a control terminal connected to the output terminal of the pulse generator and an input/output terminal connected to the node of the signal line. The second signal buffer reduces the falling transition time of a signal propagating on the signal line in response to a first control signal.

Abstract: A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.

Abstract: Disclosed in this invention are: an expression vector for the secretive production of human interferon alpha (hIFN&agr;) comprising a polynucleotide encoding a modified E. coli thermostable enterotoxin II signal sequence and a polynucleotide encoding hIFN&agr;) ligated to the 3′-end thereof; a microorganism transformed with the expression vector, and a process for secretively producing human interferon by culturing the microorganism, said process being capable of secreting a soluble form of active hIFN&agr;), which does not contain an additional methionine residue at its N-terminal, into the periplasm of an E coli cell.

Abstract: A double gate MOS transistor includes a substrate active region defined in a semiconductor substrate and a transistor active region located over the substrate active region and overlapped with the substrate active region. At least one semiconductor pillar penetrates the transistor active region and is in contact with the substrate active region. The semiconductor pillar supports the transistor active region so that the transistor active region is spaced apart from the substrate active region. At least one bottom gate electrode fills a space between the transistor active region and the substrate active region. The bottom gate electrode is insulated from the substrate active region, the transistor active region and the semiconductor pillar. At least one top gate electrode crosses over the transistor active region and has at least one end that is in contact with a sidewall of the bottom gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.

Abstract: An integrated management method for multimedia contents integratedly managing a plurality of multimedia players to replay multimedia files, with reference to file information of the multimedia files registered in a predetermined file information database (DB). The integrated management method includes activating a file search window in which a list of the multimedia files is displayed, and a file information registration window in which a list of the file information of the multimedia files is displayed. The integrated management method also includes registering the file information of the multimedia files in the file information DB by dragging and dropping the multimedia files displayed in the file search window to the file information registration window. Thus, provided are an integrated management method and an integrated management system for multimedia contents enabling file information of a multimedia file to be conveniently registered through the integrated manager for the multimedia contents.

Abstract: MOS transistors have an active region defined in a portion of a semiconductor substrate, a gate electrode on the active region, and drain and source regions in the substrate. First and second lateral protrusions extend from the lower portions of respective sidewalls of the gate electrode. The drain region has a first lightly-doped drain region under the first lateral protrusion, a second lightly-doped drain region adjacent the first lightly-doped drain region, and a heavily-doped drain region adjacent to the second lightly-doped drain region. The source region similarly has a first lightly-doped source region under the second lateral protrusion, a second lightly-doped source region adjacent the first lightly-doped source region, and a heavily-doped source region adjacent to the second lightly-doped source region. The second lightly-doped regions are deeper than the first lightly-doped regions, and the gate electrode may have an inverted T-shape.

Abstract: Disclosed is a method of outputting a list of information stored in a memory of a portable cellular telephone, comprising the steps of: determining if a list key arranged in a key input section of the portable cellular telephone is depressed; and outputting the information stored in the memory in such a fashion that the information is listed when the list key is depressed. The portable cellular telephone for implementing the method according to the present invention provides an advantage that once a user depresses only one list key arranged on the key input section of the portable cellular telephone, as a list of telephone number information is simply and easily outputted in order, thereby offering convenience to the user in use of the portable cellular telephone.

Abstract: An integrated circuit structure can include an isolation structure that electrically isolates an active region of an integrated circuit substrate from adjacent active regions and an insulation layer that extends from the isolation structure to beneath the active region. An epitaxial silicon layer extends from the active region through the insulation layer to a substrate beneath the insulation layer.

Abstract: An electric energy storage device for reducing electric resistance between the anode/cathode electrodes and their terminals is disclosed. In the electric energy storage device, an anode electrode and a cathode electrode are stacked to have offset areas with predetermined margins and an insulating film is inserted therebetween. And, the stacked electrodes between which the insulating film is inserted is rolled up so as to form an electrode body. A plate type anode terminal and a plate type cathode terminal which have the thread-like unevenness at their bottoms are connected to a top and bottom of the rolled electrode body respectively. A metal layer is formed on both contact areas of the anode and cathode electrodes by plasma or arc spray.

Abstract: A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.

Abstract: Transistors of a semiconductor device are fabricated by forming a plurality of gate electrodes on a semiconductor substrate. The gate electrodes are used as an ion implantation mask. A first impurity is ion implanted below the exposed surface of the semiconductor substrate to form first impurity regions. A second impurity is ion implanted in two directions by tilting the implantation to a predetermined angle to thereby form second impurity regions separated from the first impurity regions. The second impurity regions are formed below the channel region under the gate electrodes. The second impurity regions may overlap to provide a higher impurity concentration below a portion of the channel.

Abstract: Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

Abstract: A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed thereon, a first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate less than half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer as a mask.