Abstract: A method for treating a polyimide surface which includes the steps of amine-treating the polyimide surface and drying the thusly amine-treated polyimide surface. The amine-treating step is preferably carried out by immersing the polyimide in an amine solution which includes an amine and a solvent. The amine is preferably an aliphatic, aromatic, or siloxane amine. The drying step is preferably carried out a temperature of about 50.degree.-200.degree. C. The polyimide is preferably a polyimide having at least one imide functional group in its main chain, and is most preferably a polycondensate of at least one dianhydride and at least one diamine.

Abstract: A semiconductor memory device having a plurality of memory blocks and a plurality of I/O control circuits operatively associated with respective ones of the memory blocks. Each of the I/O control circuits includes a flash write enable signal generator responsive to a flash write mode indication signal and a respective memory block address signal, for generating a memory block specific flash write enable signal. Each of the I/O control circuits further includes a plurality of first column selectors connected between respective first alternate pairs of bit lines and respective first data input/output lines, a plurality of second column selectors connected between respective second alternate pairs of bit lines and respective second data input/output lines, and a plurality of flash write control logic circuits responsive to the memory block specific flash write enable signal and a respective one of a plurality of column select signals for generating a corresponding plurality of column selector drive signals.

Abstract: A method of reflowing a semiconductor device to increase the planarization thereof includes the steps of first forming a first insulating layer over a silicon semiconductor substrate, forming at least one electrode over the first insulating layer, and then forming a second insulating layer over the at least one electrode and the first insulating layer. A first borophospho silicate glass (BPSG) layer of low concentration is then formed over the resultant surface to a thickness of 6000 to 9000 .ANG. and containing 3-4 wt. % boron and 5-7 wt. % phosphorous. A second borophospho silicate glass (BPSG) layer of high concentration is formed over the resultant surface of the first borophospho silicate glass (BPSG) layer to a thickness of 2000 to 6000 .ANG. and containing 4-7 wt. % boron and 8-10 wt. % phosphorous.

Abstract: A video pixel presentation rate expansion circuit is provided for use with a high-resolution display system. The overall display system includes a high-resolution monitor, a computer for providing control signals, including a high-resolution frame buffer for storing computer graphics and TV video images and reading out said video data at a rate controlled by said control signals and providing said data with a high-resolution monitor for display. The expansion circuit of the present invention comprises means responsive to an expansion pattern generated by the computer for changing the time base of the video pixel data read out of said frame buffer. Circuit includes means responsive to said expansion pattern for selectively repeating predetermined scan lines of said video display and for selectively repeating certain pixel along a given scan line to match the time base of the video data read out of said frame buffer to the time base of said high-resolution monitor.