Abstract: The disclosure relates to a III-nitride semiconductor light emitting device comprising: a first semiconductor region having a first conductivity; a second semiconductor region having a second conductivity different from the first conductivity; and an active region which is interposed between the first semiconductor region and the second semiconductor region, has an InxGa1-xN (0.1?x?0.2) region that generates light, and emits red light with an emission peak wavelength of 600 nm or more, and a method for emitting red light using the device.

Abstract: A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region.

Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.

Abstract: A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

Abstract: Disclosed is a binary neural network hardware apparatus. The binary neural network hardware apparatus includes a sense amplifier configured to compare a bit line voltage of a bit line with a predetermined reference voltage; an input unit configured to input the bit line voltage to the sense amplifier; and a threshold voltage regulator configured to be connected to an artificial intelligence binary synapse through the bit line and change the bit line voltage in multiple levels.

Abstract: This disclosure generally relates to a method for manufacturing a Group III-nitride semiconductor light emitting structure. In particular, it relates to a method for manufacturing a Group III-nitride semiconductor light emitting structure capable of shifting the emission wavelength towards to a longer wavelength through an appropriate barrier (the Group III-nitride semiconductor is composed of a compound of Al(x)Ga(y)In(1-x-y)N (0?x?1, 0?y?1, 0?x+y?1)).

Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

Abstract: A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.

Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.

Abstract: The present invention provides an optical filter for its use. In the present invention, it is possible to provide an optical filter that effectively blocks ultraviolet ray and infrared ray and exhibits high transmittance in visible light. Furthermore, it is possible to provide an optical filter where the transmission characteristics are stably maintained even when an incident angle is changed. Moreover, it is possible to provide an optical filter that does not exhibit problems such as ripple or petal flare.

Abstract: The present invention provides an optical filter for its use. In the present invention, it is possible to provide an optical filter that effectively blocks ultraviolet ray and infrared ray and exhibits high transmittance in visible light. Furthermore, it is possible to provide an optical filter where the transmission characteristics are stably maintained even when an incident angle is changed. Moreover, it is possible to provide an optical filter that does not exhibit problems such as ripple, petal flare, and curl.

Abstract: The provided is an optical filter for its use. In the present invention, it is possible to provide an optical filter that effectively blocks ultraviolet ray and infrared ray and exhibits high transmittance in visible light. Furthermore, it is possible to provide an optical filter where the transmission characteristics are stably maintained even when an incident angle is changed. Moreover, it is possible to provide an optical filter that does not exhibit problems such as ripple and petal flare, and thus to provide the optical filter with excellent durability.

Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

Abstract: A semiconductor device includes a gate stack structure including insulating patterns and conductive patterns which are alternately stacked, a first separation structure penetrating the gate stack structure, a second separation structure penetrating the gate stack structure and being adjacent to the first separation structure, first and second memory channel structures penetrating the gate stack structure and disposed between the first separation structure and the second separation structure, a first bit line overlapping with the first and second memory channel structures and electrically connected to the first memory channel structure, and a second bit line overlapping with the first and second memory channel structures and the first bit line and electrically connected to the second memory channel structure.

Abstract: A semiconductor memory device includes a gate stack structure including insulating layers, a lower selection line and word lines, the word lines including a first word line adjacent to the lower selection line and a second word line on the first word line, a memory channel structure penetrating the gate stack structure, a plurality of first contact plugs electrically connected to the first word line, a plurality of second contact plugs electrically connected to the second word line, a first conductive line connected to the plurality of first contact plugs, and a second conductive line connected to one of the plurality of second contact plugs.

Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

Abstract: A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.

Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.