Abstract: A semiconductor device includes gate electrodes spaced apart from each other in a first direction perpendicular to a substrate's upper surface, and extending by different lengths in a second direction perpendicular to the first direction. The device further includes first and second channels penetrating the gate electrodes and extending in the first direction, a horizontal portion disposed in lower portions of the gate electrodes and connecting lower portions of the first and second channels to each other, and a source line disposed in an upper portion of the second channel and connected to the second channel. The gate electrodes include memory cell electrodes included in memory cells, a first ground select electrode disposed in lower portions of the memory cell electrodes, a second ground select electrode disposed in upper portions of the memory cell electrodes, and a string select electrode disposed in upper portions of the memory cell electrodes.

Abstract: A three-dimensional (3D) semiconductor memory device includes a substrate that includes a cell array region and a connection region, a dummy trench formed on the connection region, an electrode structure on the substrate and that includes vertically stacked electrodes that have a staircase structure on the connection region, a dummy insulating structure disposed in the dummy trench, the dummy insulating structure including an etch stop pattern spaced apart from the substrate and the electrode structure, a cell channel structure disposed on the cell array region and that penetrates the electrode structure and makes contact with the substrate, and a dummy channel structure disposed on the connection region and that penetrates the electrode structure and a portion of the dummy insulating structure and that makes contact with the etch stop pattern.

Abstract: A vertical memory device is provided. The vertical memory device includes a substrate, first gate electrodes, a channel, first wirings, and second wirings. The substrate includes a cell region and a peripheral circuit region. The first gate electrodes are spaced apart from each other in a first direction on the cell region of the substrate, the first direction being substantially perpendicular to the substrate. The channel extends through a portion of the first gate electrodes in the first direction on the cell region. The first wirings are formed on the cell region, and are disposed at first levels that are higher in the first direction than gate electrode levels on which the first gate electrodes are respectively formed. The second wirings are formed on the peripheral circuit region, and are disposed at the first levels and at a second level that is higher than the gate electrode levels.

Abstract: A semiconductor device according to an embodiment may include: a light emitting structure; a light transmitting electrode layer disposed on the light emitting structure; and a reflective layer disposed on the light transmitting electrode layer and including a plurality of first openings and a plurality of second openings. The semiconductor device according to the embodiment may include: a first electrode in contact with a first conductivity type semiconductor layer of the light emitting structure; and a second electrode in contact with the light transmitting electrode layer through the plurality of first openings.

Abstract: A semiconductor memory device includes a body conductive layer that includes a cell array portion and a peripheral circuit portion, an electrode structure on the cell array portion of the body conductive layer, vertical structures that penetrate the electrode structure, a residual substrate on the peripheral circuit portion of the body conductive layer, and a connection conductive pattern penetrating the residual substrate. The electrode structure includes a plurality of electrode that are stacked on top of each other. The vertical structures are connected to the cell array portion of the body conductive layer. The connection conductive pattern is connected to the peripheral circuit portion of the body conductive layer.

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a memory cell region and an insulator on a portion of the memory cell region. The semiconductor memory device includes a stress relief material that is in the insulator and is between the memory cell region and another region of the semiconductor memory device.

Abstract: A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.

Abstract: An electrode structure includes a plurality of electrodes vertically stacked on a substrate. Each of the plurality of electrodes includes an electrode portion, a pad portion and a protrusion. The electrode portion is parallel to a top surface of the substrate, extending in a first direction. The pad portion extends from the electrode portion in an inclined direction with respect to the top surface of the substrate. The protrusion protrudes from a portion of the pad portion in a direction parallel to the inclined direction. Protrusions of the plurality of electrodes are arranged in a direction diagonal to the first direction when viewed from a plan view.

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. A three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate, the electrode structure having a stepwise portion on the connection region, an etch stop structure on the stepwise portion of the electrode structure, and a plurality of contact plugs on the connection region, the contact plugs penetrating the etch stop structure and connected to corresponding pad portions of the electrodes, respectively, may be provided. The etch stop structure may include an etch stop pattern and a horizontal dielectric layer, which has have a uniform thickness and covers a top surface and a bottom surface of an etch stop pattern.

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor memory device comprises a substrate that includes a cell array region and a connection region, an electrode structure that includes a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate and has a stepwise structure on the connection region, an etch stop pattern that covers the stepwise structure of the electrode structure. The electrode structure and the etch stop pattern extend in a first direction when viewed in plan. The electrode structure has a first width in a second direction intersecting the first direction. The etch stop pattern has a second width in the second direction. The second width is less than the first direction.

Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.

Abstract: The present invention relates to an electrode assembly and a method for manufacturing the same, and more particularly, to an electrode assembly which is capable of improving an alignment of a secondary battery, realizing a high-capacity battery, and simplifying manufacturing processes of the secondary battery, and a method for manufacturing the same. The electrode assembly includes an electrode stack in which a plurality of first electrodes spaced apart from each other are disposed between two separators and second electrodes attached to both outer surfaces of the electrode stack at alternate positions of a plurality of positions on which the first electrodes are disposed, wherein, in the electrode stack, an area between the first electrode and the adjacent first electrode is folded.

Abstract: The light emitting device package disclosed in the embodiment includes: first and second frames having first and second through holes; a body disposed between the first and second frames; a light emitting device including a first bonding pad and a second bonding pad; and a conductive part in the first and second through holes. wherein at least one of the first and second bonding pads faces the first and second frames and overlaps with the first and second through holes and includes a contact region contacting the conductive part and a first non-contact non-contacting the conducive part.

Abstract: A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.

Abstract: Disclosed is a device for notching, at an interval of a unit electrode, a continuous electrode sheet in which an electrode active material is applied to one or both surfaces thereof, to form a plurality of unit electrodes from the electrode sheet, the device including a press to press notches on the top and the bottom of the electrode sheet at a set position, and two or more grippers arranged at the rear of the press based on a feed direction of the electrode sheet, the grippers drawing and transporting the electrode sheet by one pitch, a size corresponding to the unit electrode according to operation of the press, wherein while one of the grippers draws and transports the electrode sheet, the remaining grippers move to a position for drawing.

Abstract: Disclosed is a Group III nitride semiconductor template for a 300-400 nm near-ultraviolet light emitting semiconductor device, the template including: a growth substrate; a nucleation layer based on AlxGa1-xN (0<x?1, x>y); and a monocrystalline Group III nitride semiconductor layer based on AlyGa1-yN (y>0), and a near-ultraviolet light emitting semiconductor device using the template.

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a memory cell region and an insulator on a portion of the memory cell region. The semiconductor memory device includes a stress relief material that is in the insulator and is between the memory cell region and another region of the semiconductor memory device.

Abstract: A three-dimensional semiconductor device is disclosed. The device may include an electrode structure that can include a plurality of electrodes that are stacked on a substrate and extend in a first direction. Vertical structures can penetrate the electrode structure to provide a plurality of columns spaced apart from each other in a second direction crossing the first direction. The plurality of columns can include first and second edge columns located adjacent to respective opposite edges of the electrode structure, and the plurality of columns can include a center column located between the first and second edge columns. Distances between adjacent ones of the plurality of columns can decrease in a direction from the first and second edge columns toward the center column.

Abstract: The embodiments of the present invention relate to a light emitting device, a method for manufacturing a light emitting device, a light emitting device package, and a lighting device. A light emitting device according to an embodiment has: a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; a passivation layer disposed on the light emitting structure; and an insulating reflective layer disposed on the passivation layer. The passivation layer may include a first region disposed on an upper surface of the light emitting structure, and a second region disposed on side surfaces of the first conductivity type semiconductor layer, the second conductivity type semiconductor layer, and the active layer.

Abstract: A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.