Abstract: Packaged integrated circuit devices include a package substrate and a multi-chip stack of integrated circuit devices on the package substrate. The multi-chip stack includes at least one chip-select rerouting conductor. This rerouting conductor extends from the package substrate to a chip pad on an upper one of the chips in the multi-chip stack. The chip-select rerouting conductor extends through a first via hole in a lower one of the chips in the multi-chip stack.

Abstract: A method of forming a bump may involve providing a seed layer on a contact pad of a wafer. A shielding layer and a photosensitive mask layer may be formed on the seed layer. The photosensitive mask layer may be exposed and developed to form a mask pattern. An exposed portion of the shielding layer may be removed. The bump may be formed by plating the exposed seed layer.

Abstract: An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.

Abstract: In the manufacture of a semiconductor device, a photosensitive layer is deposited to cover an exposed portion of an electrode with the photosensitive layer. The photosensitive layer is then subjected to a photolithography process to partially remove the photosensitive layer covering the electrode. The electrode may be a ball electrode or a bump electrode, and the semiconductor device may be contained in a wafer level package (WLP) or flip-chip package.

Abstract: Methods of forming integrated circuit chips include forming a plurality of criss-crossing grooves in a semiconductor wafer having a plurality of contact pads thereon and filling the criss-crossing grooves with an electrically insulating layer. The electrically insulating layer is then patterned to define at least first and second through-holes therein that extend in a first one of the criss-crossing groves. The first and second through-holes are then filled with first and second through-chip connection electrodes, respectively. The semiconductor wafer is then diced into a plurality of integrated circuit chips by cutting through the electrically insulating layer in a criss-crossing pattern that overlaps with the locations of the criss-crossing grooves.

Abstract: Provided is a method for manufacturing WLCSP devices that includes preparing at least two wafers, each wafer having a plurality of corresponding semiconductor chips, each semiconductor chip having through electrodes formed in the peripheral surface region, forming or applying a solid adhesive region to a central surface region, stacking a plurality of wafers and attaching corresponding chips provided on adjacent wafers with the solid adhesive region and connecting corresponding through electrodes of adjacent semiconductor chips, dividing the stacked wafers into individual chip stack packages, and injecting a liquid adhesive into a space remaining between adjacent semiconductor chips incorporated in the resulting chip stack package. By reducing the likelihood of void regions between adjacent semiconductor chips, it is expected that a method according to the exemplary embodiments of the present invention exhibit improved mechanical stability and reliability.

Abstract: A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.

Abstract: There is provided a semiconductor device having a silicon oxynitride passivation layer and a fabrication method thereof. The passivation layer is formed of a silicon oxynitride having a dielectric constant of 5.0-6.0 and an atomic composition ratio of silicon (25-40%), oxygen (25-40%), and nitrogen (25-40%). Therefore, the passivation layer has a low dielectric constant and is highly moisture-resistant to thereby reduce the parasitic capacitance between metal wiring layers.

Abstract: A method for bonding a semiconductor chip to a lead frame in a LOC type semiconductor package in which a plurality of inner leads are bonded to an active surface of the semiconductor chip. A semiconductor chip is prepared with a partially-cured polyimide layer on the active surface. One or more strips of polyimide tape is attached to the inner leads. The semiconductor chip is attached to the inner leads by making an intermediate pressure bond between the polyimide tape and the partially-cured polyimide coating layer on the active surface. The polyimide coating layer is then cured.

Abstract: A process for producing semiconductor devices using ultraviolet sensitive tape including the steps of forming a plurality of chips on a first surface of a semiconductor wafer, adhering an ultraviolet sensitive tape to the first surface of the semiconductor wafer, back lapping a second surface of the wafer, opposite to the first surface, and irradiating the ultraviolet sensitive tape with ultraviolet rays to release the ultraviolet sensitive tape from the wafer.

Abstract: A method for manufacturing semiconductor chip package comprising steps of: (a) preparing a lead frame which comprises a pair of opposing side rails which have a plurality of through holes on their upper surface; a die pad onto which a chip will be mounted; a pair of rows of leads, each row being disposed at both sides of the die pad at a distance; and tiebars for mechanically and integrally connecting said die pad to said side rails; (b) filling a resin compound between leads and curing the resin compound to make dambars; (c) attaching said chip to an upper surface of said die pad, and electrically connecting said chip to leads; (d) encapsulating said chip, said die pad, said dambars, a part of said leads and a part of said tiebars to give a package body which is still attached to said lead frame; and (e) cutting said tiebars from lead frame to separate an individual package; and (f) forming leads extending from the package to have an appropriate bend shape is provided.

Abstract: A method for treating a polyimide surface which includes the steps of amine-treating the polyimide surface and drying the thusly amine-treated polyimide surface. The amine-treating step is preferably carried out by immersing the polyimide in an amine solution which includes an amine and a solvent. The amine is preferably an aliphatic, aromatic, or siloxane amine. The drying step is preferably carried out a temperature of about 50.degree.-200.degree. C. The polyimide is preferably a polyimide having at least one imide functional group in its main chain, and is most preferably a polycondensate of at least one dianhydride and at least one diamine.