Abstract: The present invention relates to a semiconductor memory device having a sense amplifier operated by a given control signal and a sense amplifier driver. A comparator compares the amplified sense amplifier driver with a reference voltage. A comparison output signal is enabled and used by a bias circuit and a sense amplifier driver control circuit, which circuit has an output line connected to a control terminal of the sense amplifier driver. The output line signal variably controls current flowing into the sense amplifier driver by allowing the amount of current to be increased when transmitting data from a RAM port to a SAM port. A bias circuit maintains the current flowing into the driving element at a constant state regardless of an increment or decrement of an external power supply voltage.

Abstract: The present invention relates to a semiconductor memory device and more particularly to a sense amplifier control circuit capable of stabilizing memory cell voltage characteristics by clamping an external power supply voltage to an internal power supply voltage. The semiconductor memory device according to the present invention has a sense amplifier operated by a given control signal and a first sense amplifier driver. A sense amplifier driver control circuit has an output line connected to a control terminal of the first sense amplifier driver for variably controlling current flowing into the first sense amplifier driver by allowing the amount of current to be increased when transmitting data from a RAM port to a SAM port. A bias circuit has an output line connected to a control terminal of a driving element of the sense amplifier driver control unit and maintains the current flowing into the driving element at a constant state regardless of an increment or decrement of an external power supply voltage.

Abstract: A semiconductor memory device having a plurality of memory blocks and a plurality of I/O control circuits operatively associated with respective ones of the memory blocks. Each of the I/O control circuits includes a flash write enable signal generator responsive to a flash write mode indication signal and a respective memory block address signal, for generating a memory block specific flash write enable signal. Each of the I/O control circuits further includes a plurality of first column selectors connected between respective first alternate pairs of bit lines and respective first data input/output lines, a plurality of second column selectors connected between respective second alternate pairs of bit lines and respective second data input/output lines, and a plurality of flash write control logic circuits responsive to the memory block specific flash write enable signal and a respective one of a plurality of column select signals for generating a corresponding plurality of column selector drive signals.