Abstract: Disclosed are a method and an apparatus for transmitting and receiving a signal including cell information in a communication system. An operation method of a terminal comprises the steps of: receiving a first SS/PBCH block from a base station; receiving a second SS/PBCH block from the base station after receiving the first SS/PBCH block; and confirming information included in the first SS/PBCH block and the second SS/PBCH block by performing a combining operation on the first SS/PBCH block and the second SS/PBCH block when a transmission beam of the first SS/PBCH block is the same as a transmission beam of the second SS/PBCH block. Therefore, the performance of a communication system can be improved.

Abstract: A monitoring circuit according to an embodiment of the present disclosure includes a booster configured to amplify a current amount between a terminal to which a power voltage is applied and a ground terminal to generate a sensing voltage, and an oscillator configured to output a sensing signal of which a frequency is adjusted in response to the sensing voltage, wherein the booster includes a transistor having a first size and a transistor having a second size greater than the first size, and wherein the oscillator includes a plurality of transistors having a third size greater than the first size.

Abstract: The present invention relates to a leveler capable of efficiently filling the inside of via holes formed during the manufacturing process of a printed circuit board, and an electroplating composition comprising the same. When via holes on a substrate are filled with the electroplating composition according to the present invention, the via holes can be filled in a relatively short time while minimizing the formation of dimples or voids.

Abstract: The present invention relates to a leveling agent and an electrolytic composition comprising the same. When the via hole in the substrate is filled with the electrolytic composition according to the present invention, the via hole can be filled within a relatively short time while minimizing the formation of dimples or voids.

Abstract: The present invention relates to a leveling agent and an electrolytic composition comprising the same. When the via hole in the substrate is filled with the electrolytic composition according to the present invention, the via hole can be filled within a relatively short time while minimizing the formation of dimples or voids.

Abstract: The present invention relates to a release layer for a metal foil with carrier and a metal foil with carrier including the release layer. The release layer is designed for easy removal of the carrier and includes one or more nitrogenous heterocyclic compounds and one or more inorganic compounds containing at least one metal selected from the group consisting of nickel, molybdenum, cobalt, phosphorus, manganese, and iron.

Abstract: Disclosed are a method and an apparatus for transmitting or receiving feedback information in a communication system. An operation method of a terminal comprises the steps of: receiving, from a base station, DCI #1 including scheduling information of PDSCH #1 and transmission resource information of HARQ response #1 with respect to PDSCH #1; receiving, from the base station, DCI #2 including scheduling information of PDSCH #2 and transmission resource information of HARQ response #2 with respect to PDSCH #2; and when the transmission resource information of HARQ response #1 is configured as undefined, transmitting, to the base station, HARQ response #1 and HARQ response #2 by using a resource indicated by the transmission resource information of HARQ response #2. Therefore, the performance of the communication system can be improved.

Abstract: An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.

Abstract: An electroluminescent display device includes an electroluminescent display device includes a substrate; a first pixel row on the substrate including a first plurality of pixels arranged along a first direction; a second pixel row on the substrate including a second plurality of pixels arranged along the first direction, the second pixel row being spaced apart from the first pixel row in a second direction; a first groove between the first and second pixel rows; and a light emitting diode in each pixel of the first and second pixel rows, wherein the first groove includes a first portion at one end of the first pixel row, a second portion at the other end of the first pixel row and a third portion between the first and second portions, and wherein third portion is smaller than the first portion and greater than the second portion.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

Abstract: A method and an apparatus for transmitting/receiving a signal by using a variable band width in a communication system are disclosed. An operating method of a terminal comprises the steps of: receiving, from a base station, first configuration information about one or more guard bands of an unlicensed band; confirming the one or more guard bands configured in the unlicensed band on the basis of the first configuration information; and confirming a plurality of RB sets configured in the unlicensed band on the basis of the one or more guard bands. Therefore, performance of the communication system can be improved.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: A data transmission circuit may include a plurality of data transmission lines configured to transmit a victim data signal through a victim data transmission line, and transmit an adjacent data signal through an adjacent data transmission line disposed adjacent to the victim data transmission line; and a data input/output circuit configured to control a reference voltage level reflected into the victim data signal on the basis of data pattern information of the adjacent data signal, and compare the victim data signal to the reference voltage level and output the comparison result.

Abstract: A monitoring circuit according to an embodiment of the present disclosure includes a booster configured to amplify a current amount between a terminal to which a power voltage is applied and a ground terminal to generate a sensing voltage, and an oscillator configured to output a sensing signal of which a frequency is adjusted in response to the sensing voltage, wherein the booster includes a transistor having a first size and a transistor having a second size greater than the first size, and wherein the oscillator includes a plurality of transistors having a third size greater than the first size.

Abstract: A digital counter includes: a plurality of flip-flops configured to generate a plurality of count signals; and a controller configured to prevent level transition of an input terminal of a flip-flop to generate a count signal corresponding to a least significant bit (LSB), in response to a clock signal and a count end signal.

Abstract: A semiconductor device with OTP memory cell includes a first switching unit for transferring a first bias voltage, a first MOS transistor having a first gate coupled to a first gate signal and a first terminal coupled to the first bias voltage by the first switching unit, and a second switching unit for coupling a second terminal of the first MOS transistor to a first bit line.

Abstract: A digital counter includes: a plurality of flip-flops configured to generate a plurality of count signals; and a controller configured to prevent level transition of an input terminal of a flip-flop to generate a count signal corresponding to a least significant bit (LSB), in response to a clock signal and a count end signal.

Abstract: A semiconductor memory device includes a first fuse having one end coupled with a first bit line and configured to be programmed with a data, a second fuse having one end coupled with a second bit line and configured to be programmed with the data; a program controller coupled with the other ends of the first fuse and the second fuse and configured to perform a program operation on at least one of the first fuse and the second fuse in response to a program voltage, and a read controller coupled with the other ends of the first fuse and the second fuse and configured to perform a read operation on the first fuse and the second fuse in response to a read voltage.

Abstract: A semiconductor memory device includes a memory block configured to store a data inputted/outputted through a data transfer line, a data output block configured to output the data loaded on the data transfer line in response to a source clock, wherein the data output block is controlled to be coupled with the data transfer line in response to a write operation signal, a write operation signal generation block configured to generate the write operation signal in response to an operation selection signal and a reference clock lagging behind the source clock by a set time, and a data input block configured to load the data on the data transfer line in response to the write operation signal.

Abstract: A semiconductor memory device includes a first fuse having one end coupled with a first bit line and configured to be programmed with a data, a second fuse having one end coupled with a second bit line and configured to be programmed with the data; a program controller coupled with the other ends of the first fuse and the second fuse and configured to perform a program operation on at least one of the first fuse and the second fuse in response to a program voltage, and a read controller coupled with the other ends of the first fuse and the second fuse and configured to perform a read operation on the first fuse and the second fuse in response to a read voltage.