Abstract: A thin-film transistor (TFT) includes a gate electrode, a semiconductor pattern, a source electrode, and a drain electrode. The semiconductor pattern includes an active layer being overlapped with the gate electrode and a low band gap portion having a lower energy band gap than the active layer. The source and drain electrodes are spaced apart from each other to be overlapped with the semiconductor pattern. Therefore, the semiconductor pattern includes a low band gap portion having a lower energy band gap than the active layer, so that electron mobility may be increased in a channel formed along the low band gap portion so that electric characteristics of the TFT may be enhanced.

Abstract: The present invention relates to a flowering-time and/or stem elongation regulator isolated from rice, which is selected from OsMADS50, OsMADSS1, OsMADS56, OsMADS14, OsTRX1, OsVIN1, OsCOL4 and OsCOLS, a DNA construct containing the regulator, a transgenic plant, a part thereof, and plant cell transformed with the DNA construct, and method to control flowering-time and/or stem elongation using the regulator. In the present invention, the flowering-time and/or stem elongation can be controlled, and thereby, various agricultural benefits obtained.

Abstract: A data output circuit for an integrated circuit memory device includes a control circuit that is configured to generate a plurality of clock signals responsive to at least a portion of a memory column address, and a multiplexer circuit that is configured to output memory data received on input terminals thereof onto an output terminal responsive to selective invocation of the plurality of clock signals. The clock signals are invoked in an order based on the at least a portion of the memory column address.

Abstract: Disclosed is a novel concept of infrared blocking powder, that is to say, indium antimony tin oxide (IATO), which is produced by mixing indium (In), antimony (Sb), and tin (Sn) in a predetermined mixing ratio, and co-precipitating a mixture in solvent. Additionally, the present invention provides infrared blocking solution and infrared blocking material using the infrared blocking powder, which allow visible rays to transmit therethrough but effectively block near-infrared rays acting as thermic rays.

Abstract: There is provided a plasma processing apparatus including: a chamber; an insulating plate provided in an upper region in the chamber; a ground electrode provided on a sidewall of the chamber and supplied with a ground voltage; and a lower electrode provided in a lower region in the chamber on which a substrate is seated, wherein the lower electrode comprises a plurality of electrodes, and an RF voltage and the ground voltage are alternately supplied to the adjacent two electrodes, respectively.

Abstract: A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a first conductive pattern group including a gate electrode on a substrate, forming a gate insulating layer on the first conductive pattern group, forming a semiconductor layer and an ohmic contact layer on the gate insulating layer by patterning an amorphous silicon layer and an oxide semiconductor layer, forming a second conductive pattern group including a source electrode and a drain electrode on the ohmic contact layer by patterning a data metal layer, forming a protection layer including a contact hole on the second conductive pattern group, and forming a pixel electrode on the contact hole of the protection layer. The TFT substrate including the ohmic contact layer formed of an oxide semiconductor is further provided.

Abstract: A plasma processing apparatus includes: a chamber; an insulating member disposed in an upper portion of the chamber; a ground electrode formed at a side wall of the chamber, a ground potential being applied to the ground electrode; and a lower electrode disposed in a lower portion of the chamber, a substrate being placed on the lower electrode, wherein the lower electrode is divided into a plurality of electrodes. According to an aspect of the present invention, particles accumulated in the central portion on a lower surface, an edge area of an upper surface, a side, and an edge area of the lower surface of the substrate can be effectively removed.

Abstract: A plasma processing apparatus includes: a chamber; an insulating member disposed in an upper portion of the chamber; a ground electrode formed at a side wall of the chamber, a ground potential being applied to the ground electrode; and a lower electrode disposed in a lower portion of the chamber, a substrate being placed on the lower electrode, wherein the lower electrode is divided into a plurality of electrodes. According to an aspect of the present invention, particles accumulated in the central portion on a lower surface, an edge area of an upper surface, a side, and an edge area of the lower surface of the substrate can be effectively removed.

Abstract: A full-stress testable memory device having an open bit line architecture and a method of testing the memory device. The memory device of the invention includes dummy bit lines, and a voltage controller connected to the dummy bit lines. The voltage controller alternately provides a first variable control voltage and a second variable control voltage to the dummy bit lines during a test mode. In accordance with a method of testing the memory device, a fixed voltage is provided to the dummy bit lines of the edge sub-arrays during a normal operation mode. However, during a test mode, the fixed voltage being applied to the dummy bit line is replaced with a supply voltage and/or a ground voltage, so that all of the sub-arrays can be equally tested.

Abstract: A data output circuit for an integrated circuit memory device includes a control circuit that is configured to generate a plurality of clock signals responsive to at least a portion of a memory column address, and a multiplexer circuit that is configured to output memory data received on input terminals thereof onto an output terminal responsive to selective invocation of the plurality of clock signals. The clock signals are invoked in an order based on the at least a portion of the memory column address.

Abstract: A memory device, such as a DDR SDRAM, may be provided in which subsets of data output circuits of the device can be selectively enabled to allow sets of data output pins to be connected in common in a testing configuration. In some embodiments, a memory device includes a plurality of data output circuits, respective ones of which are configured to receive data from respective internal data lines and respective ones of which are coupled to respective data input/output pins. The device further includes a data output control circuit operative to selectively enable subsets of the plurality of data output circuits to drive their respective corresponding data input/output pins responsive to an externally-applied control signal. The data output control circuit may be operative to selectively cause subsets of the plurality of data output circuits to present a high impedance at their respective corresponding data input/output pins. The invention may be embodied as devices and methods.

Abstract: A full-stress testable memory device having an open bit line architecture and a method of testing the memory device. The memory device of the invention includes dummy bit lines, and a voltage controller connected to the dummy bit lines. The voltage controller alternately provides a first variable control voltage and a second variable control voltage to the dummy bit lines during a test mode. In accordance with a method of testing the memory device, a fixed voltage is provided to the dummy bit lines of the edge sub-arrays during a normal operation mode. However, during a test mode, the fixed voltage being applied to the dummy bit line is replaced with a supply voltage and/or a ground voltage, so that all of the sub-arrays can be equally tested.

Abstract: Integrated circuit memory devices include a memory cell array that is configured to write N data bits in parallel and a write data path that is configured to serially receive 2N data bits from an external terminal. The write data path includes 2N write data buffers that are configured to store the 2N data bits, 2N switches, and N data lines that are configured to connect at least N of the 2N switches to the memory cell array to write therein N data bits in parallel. A reduced number of local data lines and/or global data lines may be provided.

Abstract: An integrated circuit memory device includes a memory cell array, a plurality of data input lines configured to convey data to the memory cell array and a plurality of data output lines configured to convey data from the memory cell array. The device also includes a memory write buffer that receives write data for the memory cell array and responsively drives the data input lines, a sense amplifier and a plurality of sense amplifier input lines configured to convey data to the sense amplifier. The device further includes a selecting circuit coupled to the data input lines, to the data output lines and to the sense amplifier input lines and configured to selectively couple the data input lines to the sense amplifier input lines responsive to a control signal.

Abstract: An integrated circuit memory device includes a memory cell array, a plurality of data input lines configured to convey data to the memory cell array and a plurality of data output lines configured to convey data from the memory cell array. The device also includes a memory write buffer that receives write data for the memory cell array and responsively drives the data input lines, a sense amplifier and a plurality of sense amplifier input lines configured to convey data to the sense amplifier. The device further includes a selecting circuit coupled to the data input lines, to the data output lines and to the sense amplifier input lines and configured to selectively couple the data input lines to the sense amplifier input lines responsive to a control signal.

Abstract: Integrated circuit memory devices include a memory cell array that is configured to write N data bits in parallel and a write data path that is configured to serially receive 2N data bits from an external terminal. The write data path includes 2N write data buffers that are configured to store the 2N data bits, 2N switches, and N data lines that are configured to connect at least N of the 2N switches to the memory cell array to write therein N data bits in parallel. A reduced number of local data lines and/or global data lines may be provided.

Abstract: A memory device, such as a DDR SDRAM, may be provided in which subsets of data output circuits of the device can be selectively enabled to allow sets of data output pins to be connected in common in a testing configuration. In some embodiments, a memory device includes a plurality of data output circuits, respective ones of which are configured to receive data from respective internal data lines and respective ones of which are coupled to respective data input/output pins. The device further includes a data output control circuit operative to selectively enable subsets of the plurality of data output circuits to drive their respective corresponding data input/output pins responsive to an externally-applied control signal. The data output control circuit may be operative to selectively cause subsets of the plurality of data output circuits to present a high impedance at their respective corresponding data input/output pins. The invention may be embodied as devices and methods.

Abstract: A high vacuum apparatus for fabricating a semiconductor device includes a reactive chamber provided with an inlet and an outlet for a reactive gas, a suscepter installed in the reactive chamber for mounting the semiconductor thereon and a vacuum pump connected with the outlet to make the inside of the reactive chamber to put in a high vacuum state, wherein a gas injector of the reactive gas inlet is directed downward of the semiconductor device so that the initial gas flowing of the reactive gas injected from the reactive gas inlet does not directly pass the upper portion of the semiconductor substrate mounted on the suscepter. Since the reactive gas is prevented from cooling and condensing at the upper surface of the semiconductor substrate, defective proportion of the semiconductor device can be remarkably reduced.

Abstract: A high vacuum apparatus for fabricating a semiconductor device includes a reactive chamber provided with an inlet and an outlet for a reactive gas, a suscepter installed in the reactive chamber for mounting the semiconductor thereon and a vacuum pump connected with the outlet to make the inside of the reactive chamber to put in a high vacuum state, wherein a gas injector of the reactive gas inlet is directed downward of the semiconductor device so that the initial gas flowing of the reactive gas injected from the reactive gas inlet does not directly pass the upper portion of the semiconductor substrate mounted on the suscepter. Since the reactive gas is prevented from cooling and condensing at the upper surface of the semiconductor substrate, defective proportion of the semiconductor device can be remarkably reduced.

Abstract: Disclosed is a burst-type random access memory device with a double data rate scheme, in which at least two data is inputted/outputted to/from the memory device during a clock cycle. In the burst-type random access memory device, a first address generator is further provided, which generates a sequence of addresses in response to an externally applied initial address, wherein the first addresses correspond to a first half period of the clock cycle during a burst mode of operation, respectively. And, in the memory device, a second address generator is furthermore provided, which receives the addresses from the first address generator and generates a sequence of addresses in accordance with burst information signals each indicative of a burst length and a type of the burst mode of operation, wherein the second addresses correspond to a second half period of the clock cycle during the burst mode of operation, respectively.