Patents by Inventor Sung-Shan Tai

Sung-Shan Tai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170288034
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Application
    Filed: April 27, 2017
    Publication date: October 5, 2017
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K. Lui
  • Patent number: 9716156
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Grant
    Filed: May 2, 2015
    Date of Patent: July 25, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K Lui
  • Publication number: 20160322469
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Application
    Filed: May 2, 2015
    Publication date: November 3, 2016
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K. Lui
  • Patent number: 9337329
    Abstract: A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source and that may include a PtSi, ErSi layer and may further be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: May 10, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yongzhong Hu, Sung-Shan Tai
  • Patent number: 9214545
    Abstract: A semiconductor device has a plurality of gate electrodes over a gate insulator layer formed in active trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the semiconductor substrate and electrically connected to the gate electrodes. The first gate runner abuts and surrounds the active region. A second gate runner is connected to the first gate runner to make contact to a gate metal. A dielectric filled trench surrounds the first and second gate runners and the active region and a highly doped channel stop region is formed under the dielectric filled trench.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: December 15, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sung-Shan Tai, Sik Lui, Xiaobin Wang
  • Patent number: 9024378
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Grant
    Filed: February 9, 2013
    Date of Patent: May 5, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K Lui
  • Patent number: 9006053
    Abstract: Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD is created into side walls of TCT and beneath SCD. An embedded Shannon implant region (ESIR) is created into sub-contact trench zone (SCTZ) beneath TCT floor. A metal layer is formed in contact with ESIR, body and source region. The metal layer also fills TCT and covers dielectric region thus completing the MOSFET/SKY with only one-time etching of its TCT.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: April 14, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Ji Pan, Daniel Ng, Sung-Shan Tai, Anup Bhalla
  • Publication number: 20150097232
    Abstract: A semiconductor device has a plurality of gate electrodes over a gate insulator layer formed in active trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the semiconductor substrate and electrically connected to the gate electrodes. The first gate runner abuts and surrounds the active region. A second gate runner is connected to the first gate runner to make contact to a gate metal. A dielectric filled trench surrounds the first and second gate runners and the active region and a highly doped channel stop region is formed under the dielectric filled trench.
    Type: Application
    Filed: December 8, 2014
    Publication date: April 9, 2015
    Inventors: Sung-Shan Tai, Sik Lui, Xiaobin Wang
  • Patent number: 9000514
    Abstract: Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: April 7, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yeeheng Lee, Sung-Shan Tai, Hong Chang, John Chen
  • Patent number: 8907416
    Abstract: A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: December 9, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sung-Shan Tai, Sik Lui, Xiaobin Wang
  • Patent number: 8847306
    Abstract: A semiconductor substrate may be etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material separated by an insulator is formed over the first conductive material. A first insulator layer is formed on the trenches. A body layer is formed in the substrate. A source is formed in the body layer. A second insulator layer is formed on the trenches and source. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on the second insulator layer. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: September 30, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sung-Shan Tai, Hamza Yilmaz, Anup Bhalla, Hong Chang, John Chen
  • Patent number: 8835251
    Abstract: A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: September 16, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: YongZhong Hu, Sung-Shan Tai
  • Publication number: 20140235024
    Abstract: Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD is created into side walls of TCT and beneath SCD. An embedded Shannon implant region (ESIR) is created into sub-contact trench zone (SCTZ) beneath TCT floor. A metal layer is formed in contact with ESIR, body and source region. The metal layer also fills TCT and covers dielectric region thus completing the MOSFET/SKY with only one-time etching of its TCT.
    Type: Application
    Filed: April 29, 2014
    Publication date: August 21, 2014
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventors: Ji Pan, Daniel Ng, Sung-Shan Tai, Anup Bhalla
  • Publication number: 20140225187
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Application
    Filed: February 9, 2013
    Publication date: August 14, 2014
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K. Lui
  • Publication number: 20140179074
    Abstract: Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD is created into side walls of TCT and beneath SCD. An embedded Shannon implant region (ESIR) is created into sub-contact trench zone (SCTZ) beneath TCT floor. A metal layer is formed in contact with ESIR, body and source region. The metal layer also fills TCT and covers dielectric region thus completing the MOSFET/SKY with only one-time etching of its TCT.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Inventors: Ji Pan, Daniel Ng, Sung-Shan Tai, Anup Bhalla
  • Patent number: 8748268
    Abstract: Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD is created into side walls of TCT and beneath SCD. An embedded Shannon implant region (ESIR) is created into sub-contact trench zone (SCTZ) beneath TCT floor. A metal layer is formed in contact with ESIR, body and source region. The metal layer also fills TCT and covers dielectric region thus completing the MOSFET/SKY with only one-time etching of its TCT.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: June 10, 2014
    Assignee: Alpha to Omega Semiconductor, Inc.
    Inventors: Ji Pan, Daniel Ng, Sung-Shan Tai, Anup Bhalla
  • Patent number: 8709895
    Abstract: The present invention provides a termination structure of a power semiconductor device and a manufacturing method thereof. The power semiconductor device has an active region and a termination region. The termination region surrounds the active region, and the termination structure is disposed in the termination region. The termination structure includes a semiconductor substrate, an insulating layer and a metal layer. The semiconductor substrate has a trench disposed in the termination region. The insulating layer is partially filled into the trench and covers the semiconductor substrate, and a top surface of the insulating layer has a hole. The metal layer is disposed on the insulating layer, and is filled into the hole.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: April 29, 2014
    Assignee: Sinopower Semiconductor Inc.
    Inventors: Sung-Shan Tai, Hung-Sheng Tsai
  • Patent number: 8643094
    Abstract: A method of forming a contact opening in a semiconductor substrate is presented. A plurality of trench gates each having a projecting portion are formed in a semiconductor substrate, and a stop layer is deposited over the semiconductor substrate extending over the projecting portions, wherein each portion of the stop layer along each of the sidewalls of the projecting portions is covered by a spacer. By removing the portions of the stop layer not covered by the spacers by utilizing a relatively higher etching selectivity of the stop layer to the spacers, the openings between adjacent projecting portions with an L-type shape on each sidewall can be formed, and a lithography process can be performed to form self-aligned contact openings thereafter.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: February 4, 2014
    Assignee: Sinopower Semiconductor, Inc.
    Inventors: Sung-Shan Tai, Teng-hao Yeh, Chia-Hui Chen
  • Patent number: 8536646
    Abstract: The present invention provides a trench type power transistor device including a semiconductor substrate, at least one transistor cell, a gate metal layer, a source metal layer, and a second gate conductive layer. The semiconductor substrate has at least one trench. The transistor cell includes a first gate conductive layer disposed in the trench. The gate metal layer and the source metal layer are disposed on the semiconductor substrate. The second gate conductive layer is disposed between the first gate conductive layer and the source metal layer. The second gate conductive layer electrically connects the first gate conductive layer to the gate metal layer, and the second gate conductive layer is electrically insulated from the source metal layer and the semiconductor substrate.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: September 17, 2013
    Assignee: Sinopower Semiconductor Inc.
    Inventors: Teng-Hao Yeh, Shian-Hau Liao, Chia-Hui Chen, Sung-Shan Tai
  • Patent number: 8524558
    Abstract: This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: September 3, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sung-Shan Tai, YongZhong Hu