Patents by Inventor Sung-Wei Lin
Sung-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972974Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.Type: GrantFiled: January 13, 2022Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sung-Li Wang, Shuen-Shin Liang, Yu-Yun Peng, Fang-Wei Lee, Chia-Hung Chu, Mrunal Abhijith Khaderbad, Keng-Chu Lin
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 7813198Abstract: One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to generate a bit-line current on the bit-line node in response to a bias voltage during a read operation. The system further comprises a sense amplifier configured to maintain a substantially constant voltage magnitude of the bit-line node during a pre-charge phase and a sense phase of the read operation based on regulating current flow to and from the bit-line node, and to determine a memory value of the flash memory transistor during the read operation based on a magnitude of the bit-line current on the bit-line node.Type: GrantFiled: April 14, 2008Date of Patent: October 12, 2010Assignee: Texas Instruments IncorporatedInventors: Sung-Wei Lin, Stephen Keith Heinrich-Barna
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Patent number: 7630257Abstract: One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.Type: GrantFiled: October 4, 2006Date of Patent: December 8, 2009Assignee: Texas Instruments IncorporatedInventors: Sudhir Kumar Madan, Hugh P. Mcadams, Sung-Wei Lin
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Publication number: 20090034338Abstract: One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to generate a bit-line current on the bit-line node in response to a bias voltage during a read operation. The system further comprises a sense amplifier configured to maintain a substantially constant voltage magnitude of the bit-line node during a pre-charge phase and a sense phase of the read operation based on regulating current flow to and from the bit-line node, and to determine a memory value of the flash memory transistor during the read operation based on a magnitude of the bit-line current on the bit-line node.Type: ApplicationFiled: April 14, 2008Publication date: February 5, 2009Inventors: Sung-Wei Lin, Stephen Keith Heinrich-Barna
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Publication number: 20090010038Abstract: An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.Type: ApplicationFiled: September 19, 2008Publication date: January 8, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: SUDHIR KUMAR MADAN, SUNG-WEI LIN, JOHN FONG
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Patent number: 7463504Abstract: Methods are described for operating a FeRAM and other such memory devices in a manner that avoids over-voltage breakdown of the gate oxide in memory cells along dummy bit lines used at the edges of memory arrays, the methods comprising floating the dummy bit line during plate line pulsing activity. In one implementation of the present invention the method is applied to a FeRAM dummy cell having a plate line, a dummy bit line, a pass transistor, and a ferroelectric storage capacitor. The method comprises initially grounding the dummy bit line as a preferred pre-condition, however, this step may be considered an optional step if the storage node of the storage capacitor is otherwise grounded. The method then comprises floating the dummy bit line, activating a word line associated with the memory cell, and pulsing the plate line. Alternately, the method comprises applying a positive voltage bias to the dummy bit line in place of, or before floating the dummy bit line.Type: GrantFiled: September 15, 2005Date of Patent: December 9, 2008Assignee: Texas Instruments IncorporatedInventors: Sung-Wei Lin, Sudhir Madan
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Patent number: 7443708Abstract: An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.Type: GrantFiled: April 24, 2006Date of Patent: October 28, 2008Assignee: Texas Instruments IncorporatedInventors: Sudhir Kumar Madan, Sung-Wei Lin, John Fong
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Publication number: 20080084773Abstract: One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.Type: ApplicationFiled: October 4, 2006Publication date: April 10, 2008Inventors: Sudhir Kumar Madan, Hugh P. Mcadams, Sung-Wei Lin
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Publication number: 20080079471Abstract: A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850 ) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).Type: ApplicationFiled: November 8, 2007Publication date: April 3, 2008Applicant: Texas Instruments IncorporatedInventors: Sung-Wei Lin, Sudhir Madan, John Fong
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Patent number: 7349237Abstract: A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).Type: GrantFiled: December 3, 2004Date of Patent: March 25, 2008Assignee: Texas Instruments IncorporatedInventors: Sung-Wei Lin, Sudhir K. Madan, John Fong
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Patent number: 7301795Abstract: Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.Type: GrantFiled: October 28, 2005Date of Patent: November 27, 2007Assignee: Texas Instruments IncorporatedInventors: John Y. Fong, Anand Seshadri, Sung-Wei Lin, Sudhir Kumar Madan, Jarrod Eliason
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Publication number: 20070211510Abstract: An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.Type: ApplicationFiled: April 24, 2006Publication date: September 13, 2007Inventors: Sudhir Madan, Sung-Wei Lin, John Fong
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Publication number: 20070058413Abstract: Methods are described for operating a FeRAM and other such memory devices in a manner that avoids over-voltage breakdown of the gate oxide in memory cells along dummy bit lines used at the edges of memory arrays, the methods comprising floating the dummy bit line during plate line pulsing activity. In one implementation of the present invention the method is applied to a FeRAM dummy cell having a plate line, a dummy bit line, a pass transistor, and a ferroelectric storage capacitor. The method comprises initially grounding the dummy bit line as a preferred pre-condition, however, this step may be considered an optional step if the storage node of the storage capacitor is otherwise grounded. The method then comprises floating the dummy bit line, activating a word line associated with the memory cell, and pulsing the plate line. Alternately, the method comprises applying a positive voltage bias to the dummy bit line in place of, or before floating the dummy bit line.Type: ApplicationFiled: September 15, 2005Publication date: March 15, 2007Inventors: Sung-Wei Lin, Sudhir Madan
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Publication number: 20070038805Abstract: A scheme for dealing with or handling faulty ‘grains’ or portions of a nonvolatile ferroelectric memory array is disclosed. In one example, a grain of the memory is less than a column high and less than a row wide. A replacement operation is performed on the memory portion when a repair programming group finds that an address of the portion corresponds to a failed row address and a failed column address.Type: ApplicationFiled: August 9, 2005Publication date: February 15, 2007Inventors: Jarrod Eliason, Sudhir Madan, Sung-Wei Lin, Hugh McAdams
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Patent number: 7133304Abstract: Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.Type: GrantFiled: March 22, 2004Date of Patent: November 7, 2006Assignee: Texas Instruments IncorporatedInventors: Sudhir Kumar Madan, Sung-Wei Lin, Hugh P. McAdams, Anand Seshadri, Jarrod Eliason
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Publication number: 20060107095Abstract: Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.Type: ApplicationFiled: October 28, 2005Publication date: May 18, 2006Inventors: John Fong, Anand Seshadri, Sung-Wei Lin, Sudhir Madan, Jarrod Eliason
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Publication number: 20050207201Abstract: Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.Type: ApplicationFiled: March 22, 2004Publication date: September 22, 2005Inventors: Sudhir Madan, Sung-Wei Lin, Hugh McAdams, Anand Seshadri, Jarrod Eliason
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Publication number: 20050078504Abstract: A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).Type: ApplicationFiled: December 3, 2004Publication date: April 14, 2005Inventors: Sung-Wei Lin, Sudhir Madan, John Fong
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Patent number: 6826103Abstract: Methods and apparatus for trimming a reference circuit. A representative technique includes transmitting a constant signal (e.g., a constant current or voltage). The constant signal is received (e.g., at a device pin or other contact). The constant signal is compared to a reference signal. Variables are obtained for program/erase pulses from a user. The reference circuit signal is adjusted to match the constant signal by sending program/erase pulses to the reference circuit. The program/erase pulses are set based on the variables for program/erase pulses and a result of comparing the constant signal with the reference signal.Type: GrantFiled: October 30, 2002Date of Patent: November 30, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Nathan I. Moon, Richard K. Eguchi, Sung-Wei Lin