Patents by Inventor Sung-Wei Lin

Sung-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7813198
    Abstract: One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to generate a bit-line current on the bit-line node in response to a bias voltage during a read operation. The system further comprises a sense amplifier configured to maintain a substantially constant voltage magnitude of the bit-line node during a pre-charge phase and a sense phase of the read operation based on regulating current flow to and from the bit-line node, and to determine a memory value of the flash memory transistor during the read operation based on a magnitude of the bit-line current on the bit-line node.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: October 12, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Sung-Wei Lin, Stephen Keith Heinrich-Barna
  • Patent number: 7630257
    Abstract: One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: December 8, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Sudhir Kumar Madan, Hugh P. Mcadams, Sung-Wei Lin
  • Publication number: 20090034338
    Abstract: One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to generate a bit-line current on the bit-line node in response to a bias voltage during a read operation. The system further comprises a sense amplifier configured to maintain a substantially constant voltage magnitude of the bit-line node during a pre-charge phase and a sense phase of the read operation based on regulating current flow to and from the bit-line node, and to determine a memory value of the flash memory transistor during the read operation based on a magnitude of the bit-line current on the bit-line node.
    Type: Application
    Filed: April 14, 2008
    Publication date: February 5, 2009
    Inventors: Sung-Wei Lin, Stephen Keith Heinrich-Barna
  • Publication number: 20090010038
    Abstract: An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.
    Type: Application
    Filed: September 19, 2008
    Publication date: January 8, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: SUDHIR KUMAR MADAN, SUNG-WEI LIN, JOHN FONG
  • Patent number: 7463504
    Abstract: Methods are described for operating a FeRAM and other such memory devices in a manner that avoids over-voltage breakdown of the gate oxide in memory cells along dummy bit lines used at the edges of memory arrays, the methods comprising floating the dummy bit line during plate line pulsing activity. In one implementation of the present invention the method is applied to a FeRAM dummy cell having a plate line, a dummy bit line, a pass transistor, and a ferroelectric storage capacitor. The method comprises initially grounding the dummy bit line as a preferred pre-condition, however, this step may be considered an optional step if the storage node of the storage capacitor is otherwise grounded. The method then comprises floating the dummy bit line, activating a word line associated with the memory cell, and pulsing the plate line. Alternately, the method comprises applying a positive voltage bias to the dummy bit line in place of, or before floating the dummy bit line.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: December 9, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Sung-Wei Lin, Sudhir Madan
  • Patent number: 7443708
    Abstract: An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: October 28, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Sudhir Kumar Madan, Sung-Wei Lin, John Fong
  • Publication number: 20080084773
    Abstract: One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.
    Type: Application
    Filed: October 4, 2006
    Publication date: April 10, 2008
    Inventors: Sudhir Kumar Madan, Hugh P. Mcadams, Sung-Wei Lin
  • Publication number: 20080079471
    Abstract: A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850 ) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).
    Type: Application
    Filed: November 8, 2007
    Publication date: April 3, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Sung-Wei Lin, Sudhir Madan, John Fong
  • Patent number: 7349237
    Abstract: A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: March 25, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Sung-Wei Lin, Sudhir K. Madan, John Fong
  • Patent number: 7301795
    Abstract: Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: November 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: John Y. Fong, Anand Seshadri, Sung-Wei Lin, Sudhir Kumar Madan, Jarrod Eliason
  • Publication number: 20070211510
    Abstract: An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.
    Type: Application
    Filed: April 24, 2006
    Publication date: September 13, 2007
    Inventors: Sudhir Madan, Sung-Wei Lin, John Fong
  • Publication number: 20070058413
    Abstract: Methods are described for operating a FeRAM and other such memory devices in a manner that avoids over-voltage breakdown of the gate oxide in memory cells along dummy bit lines used at the edges of memory arrays, the methods comprising floating the dummy bit line during plate line pulsing activity. In one implementation of the present invention the method is applied to a FeRAM dummy cell having a plate line, a dummy bit line, a pass transistor, and a ferroelectric storage capacitor. The method comprises initially grounding the dummy bit line as a preferred pre-condition, however, this step may be considered an optional step if the storage node of the storage capacitor is otherwise grounded. The method then comprises floating the dummy bit line, activating a word line associated with the memory cell, and pulsing the plate line. Alternately, the method comprises applying a positive voltage bias to the dummy bit line in place of, or before floating the dummy bit line.
    Type: Application
    Filed: September 15, 2005
    Publication date: March 15, 2007
    Inventors: Sung-Wei Lin, Sudhir Madan
  • Publication number: 20070038805
    Abstract: A scheme for dealing with or handling faulty ‘grains’ or portions of a nonvolatile ferroelectric memory array is disclosed. In one example, a grain of the memory is less than a column high and less than a row wide. A replacement operation is performed on the memory portion when a repair programming group finds that an address of the portion corresponds to a failed row address and a failed column address.
    Type: Application
    Filed: August 9, 2005
    Publication date: February 15, 2007
    Inventors: Jarrod Eliason, Sudhir Madan, Sung-Wei Lin, Hugh McAdams
  • Patent number: 7133304
    Abstract: Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: November 7, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Sudhir Kumar Madan, Sung-Wei Lin, Hugh P. McAdams, Anand Seshadri, Jarrod Eliason
  • Publication number: 20060107095
    Abstract: Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.
    Type: Application
    Filed: October 28, 2005
    Publication date: May 18, 2006
    Inventors: John Fong, Anand Seshadri, Sung-Wei Lin, Sudhir Madan, Jarrod Eliason
  • Publication number: 20050207201
    Abstract: Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.
    Type: Application
    Filed: March 22, 2004
    Publication date: September 22, 2005
    Inventors: Sudhir Madan, Sung-Wei Lin, Hugh McAdams, Anand Seshadri, Jarrod Eliason
  • Publication number: 20050078504
    Abstract: A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).
    Type: Application
    Filed: December 3, 2004
    Publication date: April 14, 2005
    Inventors: Sung-Wei Lin, Sudhir Madan, John Fong
  • Patent number: 6826103
    Abstract: Methods and apparatus for trimming a reference circuit. A representative technique includes transmitting a constant signal (e.g., a constant current or voltage). The constant signal is received (e.g., at a device pin or other contact). The constant signal is compared to a reference signal. Variables are obtained for program/erase pulses from a user. The reference circuit signal is adjusted to match the constant signal by sending program/erase pulses to the reference circuit. The program/erase pulses are set based on the variables for program/erase pulses and a result of comparing the constant signal with the reference signal.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: November 30, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Nathan I. Moon, Richard K. Eguchi, Sung-Wei Lin
  • Publication number: 20040123181
    Abstract: Methods and apparatus for self-repairing non-volatile memory using a PreAllocated Redundancy (PAR) architecture. In a representative embodiment, the non-volatile memory includes a block, a memory subblock, a redundancy subblock having a size equal to the size of the memory subblock, a comparator coupled to the block, a fail latch circuit coupled to the block, and a fuse coupled to the block. The comparator is configured to identify a failure within a particular memory subblock by comparing expected data with read data. The fail latch circuit is configured to determine an address of the particular memory subblock. The fuse is configured to cause the particular memory subblock to be replaced with the redundancy subblock, thereby repairing the non-volatile memory.
    Type: Application
    Filed: December 20, 2002
    Publication date: June 24, 2004
    Inventors: Nathan I. Moon, Richard K. Eguchi, Sung-Wei Lin
  • Patent number: 6751125
    Abstract: A technique for reducing the read gate voltage in a memory array including memory cells having a transistor for storing charge indicative of the value stored in the cell. In one example, a voltage greater than the substrate voltage is applied to the sources of the transistors of the memory cells of the array to increase the threshold voltage of a transistor due the body effect. The read gate voltage is greater than the source voltage which is greater than the substrate voltage. A non read voltage of less than the source voltage is applied to the gates of the transistors of the unselected rows to reduce leakage current. With this embodiment, the threshold voltages of transistors having an erased state can be less than 0V. With some embodiments, the read disturb caused by a gate voltage can be reduced due to the reduction in the gate voltage. In other examples, a negative voltage is applied to the gates of unselected rows to prevent leakage current.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: June 15, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Erwin J. Prinz, Craig T. Swift, Jane A. Yater, Sung-Wei Lin, Frank K. Baker, Jr.