Patents by Inventor Sung Won Jun

Sung Won Jun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11145761
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: October 12, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Shiyu Sun, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Vanessa Pena, Errol Antonio C. Sanchez, Benjamin Colombeau, Michael Chudzik, Bingxi Wood, Nam Sung Kim
  • Patent number: 10573719
    Abstract: Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: February 25, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shiyu Sun, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Benjamin Colombeau, Michael Chudzik
  • Publication number: 20200035822
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Inventors: Shiyu SUN, Naomi YOSHIDA, Theresa Kramer GUARINI, Sung Won JUN, Vanessa PENA, Errol Antonio C. SANCHEZ, Benjamin COLOMBEAU, Michael CHUDZIK, Bingxi WOOD, Nam Sung KIM
  • Patent number: 10490666
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: November 26, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shiyu Sun, Nam Sung Kim, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Vanessa Pena, Errol Antonio C. Sanchez, Benjamin Colombeau, Michael Chudzik, Bingxi Wood
  • Publication number: 20180061978
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Application
    Filed: November 6, 2017
    Publication date: March 1, 2018
    Inventors: Shiyu SUN, Naomi YOSHIDA, Theresa Kramer GUARINI, Sung Won JUN, Vanessa PENA, Errol Antonio C. SANCHEZ, Benjamin COLOMBEAU, Michael CHUDZIK, Bingxi Sun WOOD, Nam Sung KIM
  • Patent number: 9865735
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: January 9, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Shiyu Sun, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Vanessa Pena, Errol Antonio C. Sanchez, Benjamin Colombeau, Michael Chudzik, Bingxi Wood, Nam Sung Kim
  • Publication number: 20170018624
    Abstract: Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Application
    Filed: September 28, 2016
    Publication date: January 19, 2017
    Inventors: Shiyu SUN, Naomi YOSHIDA, Theresa Kramer GUARINI, Sung Won JUN, Benjamin COLOMBEAU, Michael CHUDZIK
  • Publication number: 20160336405
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Application
    Filed: May 11, 2016
    Publication date: November 17, 2016
    Inventors: Shiyu SUN, Naomi YOSHIDA, Theresa Kramer GUARINI, Sung Won JUN, Vanessa PENA, Errol Antonio C. SANCHEZ, Benjamin COLOMBEAU, Michael CHUDZIK, Bingxi WOOD, Nam Sung KIM
  • Patent number: 9460920
    Abstract: Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: October 4, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shiyu Sun, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Benjamin Colombeau, Michael Chudzik
  • Publication number: 20130005118
    Abstract: Methods of forming III-V materials using metal organic chemical vapor deposition (MOCVD) with chlorine cleans operations are described. A chlorine-clean operation may further season an MOCVD process for improved throughput for high volume manufacturing.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 3, 2013
    Inventors: Sung Won Jun, Yan Wang, Hua Chung, Jiang Lu, Kuan Chien Keris Shen, Shiva Rai
  • Publication number: 20110104843
    Abstract: A method of fabricating a light emitting diode. According to embodiments of the present invention an active region comprising a plurality of gallium nitride (GaN) barrier layers and a plurality of indium gallium nitride (InGan) quantum well layers are formed over a substrate. A p-type gallium nitride layer is formed above the active region by a hydride vapor phase epitaxy (HVPE) at a high deposition rate.
    Type: Application
    Filed: July 23, 2010
    Publication date: May 5, 2011
    Applicant: Applied Materials, Inc.
    Inventor: Sung Won Jun
  • Publication number: 20100273291
    Abstract: Embodiments of the present invention generally relate to methods and apparatus for removing unwanted deposition build-up from one more interior surfaces of a substrate processing chamber after a substrate is processed in a chamber to form, for example, Group III-V materials by metal-organic chemical vapor deposition (MOCVD) deposition processes and/or hydride vapor phase epitaxial (HVPE) deposition processes. In one embodiment, a method for removing unwanted deposition build-up from one or more interior surfaces of a substrate processing chamber is provided. The method comprises depositing one or more Group III containing layers over a substrate disposed in the substrate processing chamber, transferring the substrate out of the substrate processing chamber, and pulsing a halogen containing gas into the substrate processing chamber to remove at least a portion of the unwanted deposition build-up from one or more interior surfaces of the substrate processing chamber.
    Type: Application
    Filed: March 24, 2010
    Publication date: October 28, 2010
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Olga Kryliouk, Jie Su, Kevin Griffin, Sung Won Jun, Sandeep Nijwahan, Xizi Dong, Tze Poon, Lori D. Washington, Jacob Grayson