Patents by Inventor Sung-Woo Han
Sung-Woo Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8143940Abstract: An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.Type: GrantFiled: December 31, 2008Date of Patent: March 27, 2012Assignee: Hynic Semiconductor Inc.Inventors: Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
-
Patent number: 8144530Abstract: A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.Type: GrantFiled: June 30, 2009Date of Patent: March 27, 2012Assignee: Hynix Semiconductor Inc.Inventors: Hyung-Soo Kim, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
-
Patent number: 8139480Abstract: A telecommunication method based on transmission control protocol (TCP) includes setting an initial value of a congestion window according to a communication situation of a communication network to more efficiently use uncongested bandwidth of the communication network. An IP network access unit in a telecommunication network determines a congestion window value based on a predetermined reference, and transmits the determined congestion window value to the mobile telecommunication terminal. The mobile communication terminal receives the congestion window value, and performs a TCP access for data telecommunication using the initial congestion window value in a slow start algorithm of TCP in a mobile telecommunication environment. The bandwidth of telecommunication network may be more efficiently used by setting an initial value of the congestion window according to the telecommunication situation or available bandwidth.Type: GrantFiled: February 11, 2009Date of Patent: March 20, 2012Assignee: Pantech Co., Ltd.Inventors: Hyoung Sang Park, Hyun Soo Kim, Sung Woo Han
-
Patent number: 8120416Abstract: A semiconductor integrated circuit can include a first voltage pad, a second voltage pad, and a voltage stabilizing unit that is connected between the first voltage pad and the second voltage pad. The first voltage pad can be connected to a first internal circuit, and the second voltage pad can be connected to a second internal circuit.Type: GrantFiled: July 1, 2008Date of Patent: February 21, 2012Assignee: Hynix Semiconductor Inc.Inventors: Kwan-Weon Kim, Jun-Ho Lee, Kun-Woo Park, Chang-Kyu Choi, Yong-Ju Kim, Sung-Woo Han, Jun-Woo Lee
-
Publication number: 20120026807Abstract: A semiconductor memory chip includes: a driving voltage reception unit configured to receive a power supply voltage and a ground voltage; a first data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive first data to output the driven first data through a first data line; a second data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive second data to output the driven second data through a second data line; and a MOS transistor coupled between the first data line and the second data line.Type: ApplicationFiled: January 24, 2011Publication date: February 2, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hyun Seok KIM, Sung Woo HAN, Jun Ho LEE, Boo Ho JUNG, Yang Hee KIM
-
Patent number: 8099620Abstract: A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal.Type: GrantFiled: December 30, 2008Date of Patent: January 17, 2012Assignee: Hynix Semiconductor Inc.Inventors: Hae Rang Choi, Yong Ju Kim, Sung Woo Han, Hee Woong Song, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang, Ji Wang Lee, Jae Min Jang, Chang Kun Park
-
Patent number: 8076964Abstract: A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal.Type: GrantFiled: December 3, 2009Date of Patent: December 13, 2011Assignee: Hynix Semiconductor Inc.Inventors: Ji-Wang Lee, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Jae-Min Jang, Chang-Kun Park
-
Patent number: 8035431Abstract: A Delay Locked Loop (DLL) includes a replica delay unit configured to delay an output clock to generate a feedback clock; a phase detector configured to measure a phase difference between the feedback clock and an input clock; a quantization unit configured to quantize the phase difference measured by the phase detector; and a delay unit configured to delay the input clock based on a quantization result from the quantization unit to generate the output clock.Type: GrantFiled: June 30, 2009Date of Patent: October 11, 2011Assignee: Hynix Semiconductor Inc.Inventors: Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
-
Patent number: 8026701Abstract: A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage generating unit generates a regulated voltage on the basis a reference voltage. The trimming capacitor unit controls a load capacitance of the voltage generating unit. The second buffer chain delays the clock signal using the regulated voltage as a supply voltage. The control unit adjusts the load capacitance by detecting a delay difference of clocks output from the first and second buffer chains.Type: GrantFiled: November 6, 2008Date of Patent: September 27, 2011Assignee: Hynix Semiconductor Inc.Inventors: Hyung-Soo Kim, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
-
Patent number: 8023356Abstract: A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the exterType: GrantFiled: December 16, 2008Date of Patent: September 20, 2011Assignee: Hynix Semicondutor, Inc.Inventors: Ic-Su Oh, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
-
Patent number: 7969214Abstract: A delay locked loop (DLL) circuit includes a phase detection unit configured to generate a phase detection signal by comparing a phase of a reference clock signal with a phase of a feedback clock signal. An update control apparatus is configured to generate a valid interval signal and an update control signal by determining a difference between the number of first logical values and the number of second logical values of the phase detection signal in response to the reference clock signal. A shift register configured to update a delay value granted to a delay line in response to the update control signal when the valid interval signal is enabled.Type: GrantFiled: June 29, 2009Date of Patent: June 28, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae Min Jang, Yong Ju Kim, Sung Woo Han, Hee Woong Song, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang, Hae Rang Choi, Ji Wang Lee, Chang Kun Park
-
Patent number: 7952364Abstract: A power noise detecting device includes a plurality of power lines, and a power noise detecting part configured to detect power noise by rectifying voltages of the plurality of power lines and converting the rectified voltages into effective voltages.Type: GrantFiled: December 10, 2008Date of Patent: May 31, 2011Assignee: Hynix Semiconductor Inc.Inventors: Hyung-Soo Kim, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
-
Patent number: 7936620Abstract: A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the predetermined level; a first output node voltage control unit configured to increase a voltage level of an output node when the first input transistor is turned ON; a second output node voltage control unit configured to decrease the voltage level of the output node when the second input transistor is turned ON; a third input transistor configured to increase the voltage level of the output node when an inversion signal of the input signal is equal to or less than the predetermined voltage level; and a fourth input transistor configured to decrease the voltage level of the output node when the inversion signal of the input signal is equal to or more than the predetermined voltage level.Type: GrantFiled: June 12, 2009Date of Patent: May 3, 2011Assignee: Hynix Semiconductor Inc.Inventors: Tae-Jin Hwang, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
-
Patent number: 7915939Abstract: A duty cycle correction apparatus includes a fixed delay unit configured to set a fixed delay time to a DLL clock signal and generate a delay rising clock signal; a variable delay unit configured to delay the DLL clock signal in response to a control signal and generate a delay falling clock signal; a duty cycle correction unit configured to generate a correction rising clock signal and a correction falling clock signal that are toggled in conformity with edge timing of the delay rising clock signal and the delay falling clock signal; and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal and generate the control signal.Type: GrantFiled: March 19, 2009Date of Patent: March 29, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae Min Jang, Yong Ju Kim, Sung Woo Han, Hee Woong Song, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang, Hae Rang Choi, Ji Wang Lee, Chang Kun Park
-
Publication number: 20110058433Abstract: A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a delay value for delaying the input signal based on a latency value of the input signal and the path information, and a delayer configured to delay the input signal by a delay corresponding to the delay information.Type: ApplicationFiled: December 8, 2009Publication date: March 10, 2011Inventors: Hae-Rang Choi, Yong-ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
-
Patent number: 7884659Abstract: A phase mixer includes a phase mixing unit configured to mix a phase of a first input signal and a phase of a second input signal in response to a phase control signal and output a phase mixed signal whose phase is varied by one or more units of a unit phase value, and a phase value adjusting unit configured to control an operation of the phrase mixing unit so that the unit phase value is adjusted in response to a code signal coding at least one of a process, voltage, or temperature (PVT) variation.Type: GrantFiled: December 31, 2008Date of Patent: February 8, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae-Min Jang, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Chang-Kun Park
-
Patent number: 7868667Abstract: An output driving device capable of improving a slew rate is provided. The output driving device includes a push-pull type driving unit configured with a pull-up PMOS transistor and a pull-down NMOS transistor, wherein body biases of the pull-up PMOS transistor and the pull-down NMOS transistor are controlled for control of a slew rate of an output signal of the driving unit.Type: GrantFiled: March 26, 2009Date of Patent: January 11, 2011Assignee: Hynix Semiconductor Inc.Inventors: Chang-Kun Park, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang
-
Publication number: 20110001533Abstract: A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal.Type: ApplicationFiled: December 3, 2009Publication date: January 6, 2011Inventors: Ji-Wang LEE, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Jae-Min Jang, Chang-Kun Park
-
Patent number: 7863957Abstract: A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.Type: GrantFiled: December 9, 2008Date of Patent: January 4, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae-Min Jang, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Chang-Kun Park
-
Publication number: 20100315139Abstract: A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.Type: ApplicationFiled: June 30, 2009Publication date: December 16, 2010Inventors: Hyung-Soo Kim, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park