Patents by Inventor Sung-Woo Han
Sung-Woo Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100054047Abstract: A semiconductor memory apparatus includes a clock generator configured to generate an internal clock signal, an asynchronous data input buffer configured to buffer a data input signal through a data pad to output a buffered data signal, and a synchronous data input buffer configured to buffer the buffered data signal synchronously with the internal clock signal, wherein a length of a line, through which the internal clock signal is transmitted to the synchronous data input buffer, is configured to be substantially the same with a length of a line, through which the buffered data is transmitted to the synchronous data input buffer.Type: ApplicationFiled: December 10, 2008Publication date: March 4, 2010Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Ji-Wang Lee, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Jae-Min Jang, Chang-Kun Park
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Publication number: 20100044872Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.Type: ApplicationFiled: June 29, 2009Publication date: February 25, 2010Inventors: Chang Kun PARK, Seong Hwi SONG, Yong Ju KIM, Sung Woo HAN, Hee Woong SONG, Ic Su OH, Hyung Soo KIM, Tae Jin HWANG, Hae Rang CHOI, Ji Wang LEE, Jae Min JANG
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Publication number: 20100039140Abstract: A buffer circuit of a semiconductor memory apparatus includes a buffering section configured to increase or decrease a voltage level of an output node by comparing a voltage level of an input signal with a voltage level of a reference voltage. A voltage compensation section applies a voltage to the output node in proportion to a variation of the reference voltage when the level of the reference voltage is lower than a target level.Type: ApplicationFiled: June 30, 2009Publication date: February 18, 2010Applicant: Hynix Semiconductor Inc.Inventors: Ji Wang Lee, Yong Ju Kim, Sung Woo Han, Hee Woong Song, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang, Hae Rang Choi, Jae Min Jang, Chang Kun Park
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Publication number: 20100039142Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.Type: ApplicationFiled: August 13, 2009Publication date: February 18, 2010Applicant: Hynix Semiconductor Inc.Inventors: JI WANG LEE, Yong Ju Kim, Sung Woo Han, Hee Woong Song, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang, Hae Rang Choi, Jae Min Jang, Chang Kun Park
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Publication number: 20100039099Abstract: A power noise detecting device includes a plurality of power lines, and a power noise detecting part configured to detect power noise by rectifying voltages of the plurality of power lines and converting the rectified voltages into effective voltages.Type: ApplicationFiled: December 10, 2008Publication date: February 18, 2010Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Hyung-Soo Kim, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
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Publication number: 20100034033Abstract: A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the predetermined level; a first output node voltage control unit configured to increase a voltage level of an output node when the first input transistor is turned ON; a second output node voltage control unit configured to decrease the voltage level of the output node when the second input transistor is turned ON; a third input transistor configured to increase the voltage level of the output node when an inversion signal of the input signal is equal to or less than the predetermined voltage level; and a fourth input transistor configured to decrease the voltage level of the output node when the inversion signal of the input signal is equal to or more than the predetermined voltage level.Type: ApplicationFiled: June 12, 2009Publication date: February 11, 2010Applicant: Hynix Semiconductor Inc.Inventors: Tae Jin HWANG, Yong Ju KIM, Sung Woo HAN, Hee Woong SONG, Ic Su OH, Hyung Soo KIM, Hae Rang CHOI, Ji Wang LEE, Jae Min JANG, Chang Kun PARK
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Publication number: 20100034043Abstract: A semiconductor IC device capable of power-sharing includes a first power line configured to be supplied with a first power, a second power line configured to be supplied with a second power, a switching block configured to connect the first power line with the second power line in response to a first control signal, and a power-sharing control block configured to generate the control signal in accordance with a plurality of operation command signals.Type: ApplicationFiled: December 11, 2008Publication date: February 11, 2010Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Hyung Soo Kim, Yong Ju Kim, Sung Woo Han, Hee- Woong Song, Ic Su Oh, Tae Jin Hwang, Hae Rang Choi, Ji Wang Lee, Jae Min Jang, Chang Kun Park
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Publication number: 20090303877Abstract: A telecommunication method based on transmission control protocol (TCP) includes setting an initial value of a congestion window according to a communication situation of a communication network to more efficiently use uncongested bandwidth of the communication network. An IP network access unit in a telecommunication network determines a congestion window value based on a predetermined reference, and transmits the determined congestion window value to the mobile telecommunication terminal. The mobile communication terminal receives the congestion window value, and performs a TCP access for data telecommunication using the initial congestion window value in a slow start algorithm of TCP in a mobile telecommunication environment. The bandwidth of telecommunication network may be more efficiently used by setting an initial value of the congestion window according to the telecommunication situation or available bandwidth.Type: ApplicationFiled: February 11, 2009Publication date: December 10, 2009Applicants: PANTECH CO., LTD., PANTECH & CURITEL COMMUNICATIONS, INC.Inventors: Hyoung Sang PARK, Hyun Soo Kim, Sung Woo Han
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Publication number: 20090278578Abstract: A delay locked loop circuit includes a phase detecting unit for detecting a phase difference between a reference clock signal and a feedback clock signal, and for producing a phase difference detection signal, a code generating unit for producing a digital code signal according to the phase difference detection signal, a control current generating unit for generating a control current using the digital code signal, and a current controlled delay line for producing the feedback clock signal by delaying the reference clock signal by a delay time varied by the control current.Type: ApplicationFiled: December 10, 2008Publication date: November 12, 2009Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
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Publication number: 20090267579Abstract: A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage generating unit generates a regulated voltage on the basis a reference voltage. The trimming capacitor unit controls a load capacitance of the voltage generating unit. The second buffer chain delays the clock signal using the regulated voltage as a supply voltage. The control unit adjusts the load capacitance by detecting a delay difference of clocks output from the first and second buffer chains.Type: ApplicationFiled: November 6, 2008Publication date: October 29, 2009Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Hyung-Soo KIM, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
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Publication number: 20090257301Abstract: A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the exterType: ApplicationFiled: December 16, 2008Publication date: October 15, 2009Applicant: Hynix Semiconductor, Inc.Inventors: Ic Su Oh, Yong Ju Kim, Sung Woo Han, Hee Woong Song, Hyung Soo Kim, Tae Jin Hwang, Hae Rang Choi, Ji Wang Lee, Jae Min Jang, Chang Kun Park
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Publication number: 20090243667Abstract: An output driving device capable of improving a slew rate is provided. The output driving device includes a push-pull type driving unit configured with a pull-up PMOS transistor and a pull-down NMOS transistor, wherein body biases of the pull-up PMOS transistor and the pull-down NMOS transistor are controlled for control of a slew rate of an output signal of the driving unit.Type: ApplicationFiled: March 26, 2009Publication date: October 1, 2009Inventors: Chang-Kun Park, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang
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Publication number: 20090231007Abstract: A semiconductor integrated circuit includes a voltage supplying unit that supplies a first regulated voltage and a second regulated voltage by using a first reference voltage and a second reference voltage, respectively, and a clock buffer unit that supplies an output clock clocking within a range of the first regulated voltage and the second regulated voltage.Type: ApplicationFiled: December 8, 2008Publication date: September 17, 2009Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Ic Su Oh, Yong Ju Kim, Sung Woo Han, Hee Woong Song, Hyung Soo Kim, Tae Jin Hwang, Hae Rang Choi, Ji Wang Lee, Jae Min Jang, Chang Kun Park
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Publication number: 20090231006Abstract: A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.Type: ApplicationFiled: December 9, 2008Publication date: September 17, 2009Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Jae Min Jang, Yong Ju Kim, Sung Woo Han, Hee Woong Song, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang, Hae Rang Choi, Ji Wang Lee, Chang Kun Park
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Publication number: 20090212853Abstract: An apparatus for supplying power in a semiconductor integrated circuit includes a plurality of power lines, each supplying external power to an interior of the semiconductor integrated circuit, and at least one decoupling capacitor set connected to the plurality of power lines and having a resistance value configured to be variable according to a bias voltage.Type: ApplicationFiled: December 31, 2008Publication date: August 27, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hyung-Soo Kim, Yong Ju Kim, Sung Woo Han, Hee Woong Song, Jae Min Jang, Ji Wang Lee, Chang Kun Park, Ic Su Oh, Hae Rang Choi, Tae Jin Hwang
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Publication number: 20090206901Abstract: A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit.Type: ApplicationFiled: December 11, 2008Publication date: August 20, 2009Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Hee Woong Song, Yong Ju Kim, Sung Woo Han, Jae Min Jang, Hyung Soo Kim, Ji Wang Lee, Chang Kun Park, Ic Su Oh, Hae Rang Choi, Tae Jin Hwang
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Publication number: 20090206900Abstract: A duty cycle correction circuit capable of reducing current consumption and that includes a back-bias voltage supply circuit for supplying back-bias voltages, wherein a duty cycle of an input clock is reflected on the back-bias voltages; and a buffer for adjusting the duty cycle of the input clock and configured to receive the back-bias voltages.Type: ApplicationFiled: July 7, 2008Publication date: August 20, 2009Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Hee Woong Song, Yong Ju Kim, Sung Woo Han, Jae Min Jang, Hyung Soo Kim, Ji Wang Lee, Chang Kun Park, Ic Su Oh, Hae Rang Choi, Tae Jin Hwang
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Publication number: 20090121786Abstract: A semiconductor integrated circuit can include a first voltage pad, a second voltage pad, and a voltage stabilizing unit that is connected between the first voltage pad and the second voltage pad. The first voltage pad can be connected to a first internal circuit, and the second voltage pad can be connected to a second internal circuit.Type: ApplicationFiled: July 1, 2008Publication date: May 14, 2009Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Kwan Weon Kim, Jun Ho Lee, Kun Woo Park, Chang Kyu Choi, Yong Ju Kim, Sung Woo Han, Jun Woo Lee
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Patent number: 7352719Abstract: Disclosed are a mobile communication terminal for and a method of transmitting/receiving voice messages using a packet-switched scheme. According to the present invention, it is possible to allow mobile carriers to promote the use efficiency of communication channels since mobile communication terminals transmit/receive voice messages over a data channel rather than a voice channel.Type: GrantFiled: October 27, 2004Date of Patent: April 1, 2008Assignee: Curitel Communications, Inc.Inventors: Sung-Woo Han, Jae-Yeol Lee
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Publication number: 20060035652Abstract: Disclosed is an SMS management system equipped with an additional data transfer function. The SMS management system includes a message transmission module, wherein the message transmission module includes: a capacity calculating unit for calculating the volume of the message content entered by the message input unit and calculating a residual capacity by deducting the volume from the maximum capacity of a short message; an additional data processing unit for attaching additional data to the short message within the limit of the residual capacity calculated by the capacity calculating unit; and a message transmission unit for transmitting the short message with the attached additional data processed by the additional data processing unit to the recipient's mobile station number entered by the number input unit.Type: ApplicationFiled: June 6, 2005Publication date: February 16, 2006Applicant: Pantech & Curitel Communications, Inc.Inventors: Woong-Cheol Kim, Sung-Woo Han