Abstract: Provided are a printed circuit board which can be used as a substrate for a package, a method of manufacturing the printed circuit board, and a semiconductor package using the printed circuit board, the printed circuit board including: a first substrate having a first mounting area for mounting a package substrate and a second mounting area for mounting a semiconductor element; a single layer or multi-layered circuit pattern of the first substrate; and a post bump connected to the circuit pattern, provided on an external insulating layer of the first mounting area, and having a concave upper surface.

Abstract: Provided is a semiconductor package, including: a lower package to which elements are mounted; a metal post connected to the lower package and including at least one metal material portion; and an upper package to which elements is mounted, and which is connected to the metal post via a solder ball.

Abstract: The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Abstract: The present invention relates to structure and manufacture method for multi-row lead frame and semiconductor package, the method characterized by forming a pad portion on a metal material (first step); performing a surface plating process or organic material coating following the first pattern formation (second step); forming a second pattern on the metal material (third step); and packaging a semiconductor chip following the second pattern formation (fourth step), whereby an under-cut phenomenon is minimized by applying a gradual etching.

Abstract: The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Abstract: A printed circuit board according the present embodiment includes an insulating layer; at least one circuit pattern or pad formed on the insulating layer; a solder resist having an opening section exposing the upper surface of the pad and formed on the insulating layer and a bump formed on the pad exposed through the opening section of the solder resist and having a lower area narrower than the upper area.

Abstract: A printed circuit board according to an embodiment of the present invention includes an insulating layer, a pad formed on the insulating layer and exposed through an opening section of a solder resist, a bump formed by filling an opening portion of the solder resist from top of the pad and having an narrow width than the opening of the solder resist.

Abstract: The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Abstract: The present invention relates to structure and manufacture method for multi-row lead frame and semiconductor package, the method characterized by forming a pad portion on a metal material (first step); performing a surface plating process or organic material coating following the first pattern formation (second step); forming a second pattern on the metal material (third step); and packaging a semiconductor chip following the second pattern formation (fourth step), whereby an under-cut phenomenon is minimized by applying a gradual etching.