Abstract: Provided are resistive memory devices and methods of fabricating the same. The resistive memory devices and the methods are advantageous for high integration because they can provide a multilayer memory cell structure. Also, the parallel conductive lines of adjacent layers do not overlap each other in the vertical direction, thus reducing errors in program/erase operations.

Abstract: Provided are an active metamaterial device operating at a high speed and a manufacturing method thereof. The active metamaterial device includes a first dielectric layer, a lower electrode disposed on the first dielectric layer, a second dielectric layer disposed on the lower electrode, metamaterial patterns disposed on the second dielectric layer, a couple layer disposed on the metamaterial patterns and the second dielectric layer, a third dielectric layer disposed on the couple layer, and an upper electrode disposed on the third dielectric layer.

Abstract: A pad for thermotherapy includes: a stretchable and flexible substrate; an electrode pattern positioned over the stretchable and flexible substrate, and including a plurality of light source electrodes and a linear electrode connecting the light source electrodes; light sources positioned over the electrode pattern; and a power supply unit for supplying power to the light source, wherein the linear electrode is formed longer than intervals between neighboring light source electrodes and separated from the substrate.

Abstract: Provided are an active metamaterial device operating at a high speed and a manufacturing method thereof. The active metamaterial device includes a first dielectric layer, a lower electrode disposed on the first dielectric layer, a second dielectric layer disposed on the lower electrode, metamaterial patterns disposed on the second dielectric layer, a couple layer disposed on the metamaterial patterns and the second dielectric layer, a third dielectric layer disposed on the couple layer, and an upper electrode disposed on the third dielectric layer.

Abstract: Provided are resistive memory devices and methods of fabricating the same. The resistive memory devices and the methods are advantageous for high integration because they can provide a multilayer memory cell structure. Also, the parallel conductive lines of adjacent layers do not overlap each other in the vertical direction, thus reducing errors in program/erase operations.

Abstract: A resistive memory device is provided. The resistive memory device includes a bottom electrode, a resistance-variable layer, and a top electrode. The resistance-variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance-variable layer. The resistance-variable layer includes a conductive polymer layer that reacts with the top electrode to form an oxide layer.

Abstract: A graphene oxide memory device includes a substrate, a lower electrode disposed on the substrate, an electron channel layer disposed on the lower electrode by using a graphene oxide, and an upper electrode disposed on the electron channel layer.

Abstract: A method for forming graphene includes introducing a substrate and a carbon-containing reactant source into a chamber, and radiating a laser beam onto the substrate to decompose the carbon-containing reactant source and form graphene over the substrate using carbon atoms generated by decomposition of the carbon-containing reactant source. A carbon-containing gas (methane) decomposes upon radiation of a laser beam. The carbon-containing gas has a decomposition rate on the order of femtoseconds and the laser beam has a pulse on the order of nanoseconds or more. The graphene is grown in a single layer along the surface of the substrate. Then, the graphene is selectively patterned using a laser beam to form a desired pattern.

Abstract: A memory device including a dielectric thin film having a plurality of dielectric layers and a method of manufacturing the same are provided. The memory device includes: a bottom electrode; at least one dielectric thin film disposed on the bottom electrode and having a plurality of dielectric layers with different charge trap densities from each other; and an top electrode disposed on the dielectric thin film. Therefore, a memory device, which can be readily manufactured by a simple process and can be highly integrated using its simple structure, can be provided.

Abstract: A memory device including a dielectric thin film having a plurality of dielectric layers and a method of manufacturing the same are provided. The memory device includes: a bottom electrode; at least one dielectric thin film disposed on the bottom electrode and having a plurality of dielectric layers with different charge trap densities from each other; and an top electrode disposed on the dielectric thin film. Therefore, a memory device, which can be readily manufactured by a simple process and can be highly integrated using its simple structure, can be provided.

Abstract: Provided are resistive memory devices and methods of fabricating the same. The resistive memory devices and the methods are advantageous for high integration because they can provide a multilayer memory cell structure. Also, the parallel conductive lines of adjacent layers do not overlap each other in the vertical direction, thus reducing errors in program/erase operations.

Abstract: A resistive memory device is provided. The resistive memory device includes a bottom electrode, a resistance-variable layer, and a top electrode. The resistance-variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance-variable layer. The resistance-variable layer includes a conductive polymer layer that reacts with the top electrode to form an oxide layer.

Abstract: Provided are a non-volatile memory device and a method of forming the non-volatile memory device. The non-volatile memory device includes a substrate, a lower electrode on the substrate, a diffusion barrier preventing the diffusion of a space charge on the lower electrode, a charge storage layer having a space charge limited characteristic on the diffusion barrier, and an upper electrode on the charge storage layer.

Abstract: Provided is a resistance variable non-volatile memory device using a trap-controlled Space Charge Limited Current (SCLC), and a manufacturing method thereof. The memory device includes a bottom electrode; an inter-electrode dielectric thin film diffusion prevention film formed on the bottom electrode; a dielectric thin film formed on the inter-electrode dielectric thin film diffusion prevention film and having a plurality of layers with different charge trap densities; and a top electrode formed on the dielectric thin film.

Abstract: Provided are a highly integrated organic memory device and a method of fabricating the same. The device includes an insulating substrate, a lower electrode disposed on the insulating substrate, an electron channel layer disposed on the lower electrode, and an upper electrode disposed on the electron channel layer. A bulk heterojunction formed of an electron-donor/electron-acceptor polymer is used as the electron channel layer having electrical bistability. Thus, a highly integrated organic memory device can be formed by a simple fabrication process.

Abstract: Provided is a method of manufacturing a nano size-gap electrode device. The method includes the steps of: disposing a floated nano structure on a semiconductor layer; forming a mask layer having at least one opening pattern to intersect the nano structure; and depositing a metal on the semiconductor layer exposed through the opening pattern to form an electrode, such that a nano size-gap is provided under the nano structure by the nano structure.

Abstract: A tri-gated molecular field effect transistor includes a gate electrode formed on a substrate and having grooves in a source region, a drain region and a channel region, and at least one molecule inserted between the source and drain electrodes in the channel region. The effects of the gate voltage on electrons passing through the channel can be maximized, and a variation gain of current supplied between the source and drain electrodes relative to the gate voltage can be greatly increased. Thus, a molecular electronic circuit having high functionality and reliability can be obtained.

Abstract: Provided is a method for manufacturing a nano-gap electrode device comprising the steps of: forming a first electrode on a substrate; forming a spacer on a sidewall of the first electrode; forming a second electrode on an exposed substrate at a side of the spacer; and forming a nano-gap between the first electrode and the second electrode by removing the spacer, whereby it is possible to control the nano-gap position, width, shape, and etc., reproducibly, and manufacture a plurality of nano-gap electrode devices at the same time.

Abstract: A memory device including a dielectric thin film having a plurality of dielectric layers and a method of manufacturing the same are provided. The memory device includes: a bottom electrode; at least one dielectric thin film disposed on the bottom electrode and having a plurality of dielectric layers with different charge trap densities from each other; and an top electrode disposed on the dielectric thin film. Therefore, a memory device, which can be readily manufactured by a simple process and can be highly integrated using its simple structure, can be provided.

Abstract: An organic semiconductor device and a method of fabricating the same are provided. The device includes: a first electrode; an electron channel layer formed on the first electrode; and a second electrode formed on the electron channel layer, wherein the electron channel layer comprises: a lower organic layer formed on the first electrode; a nano-particle layer formed on the lower organic layer and including predetermined sizes of nano-particles that are spaced a predetermined distance apart from each other; and an upper organic layer formed over the nano-particle layer. Accordingly, a highly integrated organic semiconductor device can be fabricated by a simple fabrication process, and nonuniformity of devices due to threshold voltage characteristics and downsizing of the device can resolved, so that a semiconductor device having excellent performance can be implemented.