Patents by Inventor Sung-Yun LEE
Sung-Yun LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240138255Abstract: Provided is a compound of Chemical Formula 1 or 2: wherein: R1 to R4 are each independently hydrogen or deuterium; n1 to n4 are an integer of 1 to 4; L1 and L2 are each independently a direct bond or a substituted or unsubstituted C6-60 arylene; and Ar1 and Ar2 are each independently a substituent of Chemical Formula 3: wherein X1 to X5 are each independently N or C(R5), wherein at least two of X1 to X5 are N; and each R5 is independently hydrogen, deuterium, a substituted or unsubstituted C1-20 alkyl, a substituted or unsubstituted C6-60 aryl, or a substituted or unsubstituted C2-60 heteroaryl containing at least one of N, O and S, or two adjacent R5s combine to form a benzene ring; and an organic light emitting device including the same. The device exhibits significantly superior efficiency and lifespan.Type: ApplicationFiled: February 28, 2022Publication date: April 25, 2024Inventors: Dong Uk HEO, Heekyung YUN, Miyeon HAN, Jae Tak LEE, Jung Min YOON, Hoyoon PARK, Sung Kil HONG
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Publication number: 20240105604Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Inventors: Sung-Hun Lee, Seokjung Yun, Chang-Sup Lee, Seong Soon Cho, Jeehoon Han
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Patent number: 11910614Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.Type: GrantFiled: April 1, 2022Date of Patent: February 20, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang Sup Lee, Phil Ouk Nam, Sung Yun Lee, Chang Seok Kang
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Publication number: 20220410240Abstract: According to the present disclosure, a hot stamping forming method for forming components having various strength according to parts through cooling control for each position includes: setting a required strength for each product part for a sheet supplied into a multi-point forming mold device to which a plurality of forming modules are coupled; adjusting an arrangement of the plurality of forming modules according to the set required strength; and performing cooling control for each part by controlling an amount of cooling air or mist sprayed to the sheet by the air jet nozzle in order to achieve a required cooling speed for each strength part of the supplied sheet, wherein components having various shapes are formable with respect to the supplied sheet in a single mold.Type: ApplicationFiled: May 12, 2020Publication date: December 29, 2022Inventors: Sang Kon LEE, In Kyu LEE, Sung Yun LEE, Myeong Sik JEONG, Sun Kwang HWANG, Dong Yong PARK
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Patent number: 11411024Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.Type: GrantFiled: August 17, 2020Date of Patent: August 9, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Yun Lee, Jae-Hoon Jang, Jae-Duk Lee, Joon-Hee Lee, Young-Jin Jung
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Publication number: 20220223616Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.Type: ApplicationFiled: April 1, 2022Publication date: July 14, 2022Inventors: Chang Sup LEE, Phil Ouk NAM, Sung Yun LEE, Chang Seok KANG
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Patent number: 11296104Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.Type: GrantFiled: April 10, 2020Date of Patent: April 5, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang Sup Lee, Phil Ouk Nam, Sung Yun Lee, Chang Seok Kang
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Patent number: 11036904Abstract: Provided is a ternary logic synthesis method at least temporarily performed by a computer, the ternary logic synthesis method including generating a switching table with respect to pull-up and pull-down circuits using a truth table corresponding to a ternary function, converting the switching table into a sum of products (SOP) using a Quine-McCluskey algorithm, minimizing the SOP, and mapping a transistor corresponding to the SOP.Type: GrantFiled: December 13, 2019Date of Patent: June 15, 2021Assignee: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATIONInventors: Seokhyeong Kang, Sunmean Kim, Sung-Yun Lee
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Patent number: 11020705Abstract: Provided are a porous outflow pipe and an osmosis module comprising same. A porous outflow pipe for forward osmosis or pressure-retarded osmosis, according to one embodiment of the present invention, comprises: a hollow pipe provided with a plurality of first through-holes and second through-holes in the lengthwise direction through which a fluid flows in and out; a bypass pipe arranged concentrically inside the hollow pipe in the lengthwise direction; and a partitioning plate formed along the circumference of the bypass pipe, for preventing mixing of a fluid introduced through the front end side of the hollow pipe and a fluid introduced through the second through-holes.Type: GrantFiled: December 15, 2014Date of Patent: June 1, 2021Assignee: TORAY ADVANCED MATERIALS KOREA INC.Inventors: Sung Yun Lee, Yeon Ju Sim, Jong Hwa Lee
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Publication number: 20200381453Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.Type: ApplicationFiled: August 17, 2020Publication date: December 3, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-Yun LEE, Jae-Hoon JANG, Jae-Duk LEE, Joon-Hee LEE, Young-Jin JUNG
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Patent number: 10854623Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.Type: GrantFiled: July 12, 2019Date of Patent: December 1, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang Hyun You, Jin Taek Park, Taek Soo Shin, Sung Yun Lee
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Patent number: 10770473Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.Type: GrantFiled: September 5, 2018Date of Patent: September 8, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Yun Lee, Jae-Hoon Jang, Jae-Duk Lee, Joon-Hee Lee, Young-Jin Jung
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Publication number: 20200243554Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.Type: ApplicationFiled: April 10, 2020Publication date: July 30, 2020Inventors: Chang Sup LEE, Phil Ouk NAM, Sung Yun LEE, Chang Seok KANG
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Publication number: 20200235003Abstract: A semiconductor device includes a comprise a substrate including a main zone and an extension zone, vertical channels on the main zone, and an electrode structure including gate electrodes stacked on the substrate. The vertical channel structures extend in a first direction perpendicular to a top surface of the substrate. The gate electrodes include line regions and contact regions. The line regions extend from the main zone toward the extension zone along a second direction the second direction that is perpendicular to the first direction. The contact regions are on ends of the line regions and are thicker than the line regions. A spacing distance in the second direction between the contact regions is greater than a spacing distance in the first direction between the line regions.Type: ApplicationFiled: April 2, 2020Publication date: July 23, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Chung-II HYUN, Semee JANG, Sung Yun LEE
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Publication number: 20200210637Abstract: Provided is a ternary logic synthesis method at least temporarily performed by a computer, the ternary logic synthesis method including generating a switching table with respect to pull-up and pull-down circuits using a truth table corresponding to a ternary function, converting the switching table into a sum of products (SOP) using a Quine-McCluskey algorithm, minimizing the SOP, and mapping a transistor corresponding to the SOP.Type: ApplicationFiled: December 13, 2019Publication date: July 2, 2020Inventors: Seokhyeong KANG, Sunmean KIM, Sung-Yun LEE
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Patent number: 10658230Abstract: A semiconductor device includes a comprise a substrate including a main zone and an extension zone, vertical channels on the main zone, and an electrode structure including gate electrodes stacked on the substrate. The vertical channel structures extend in a first direction perpendicular to a top surface of the substrate. The gate electrodes include line regions and contact regions. The line regions extend from the main zone toward the extension zone along a second direction the second direction that is perpendicular to the first direction. The contact regions are on ends of the line regions and are thicker than the line regions. A spacing distance in the second direction between the contact regions is greater than a spacing distance in the first direction between the line regions.Type: GrantFiled: May 13, 2019Date of Patent: May 19, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Chung-Il Hyun, Semee Jang, Sung Yun Lee
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Patent number: 10629609Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.Type: GrantFiled: October 2, 2017Date of Patent: April 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang Sup Lee, Phil Ouk Nam, Sung Yun Lee, Chang Seok Kang
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Publication number: 20190341396Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.Type: ApplicationFiled: July 12, 2019Publication date: November 7, 2019Inventors: Jang Hyun YOU, Jin Taek PARK, Taek Soo SHIN, Sung Yun LEE
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Publication number: 20190273020Abstract: A semiconductor device includes a comprise a substrate including a main zone and an extension zone, vertical channels on the main zone, and an electrode structure including gate electrodes stacked on the substrate. The vertical channel structures extend in a first direction perpendicular to a top surface of the substrate. The gate electrodes include line regions and contact regions. The line regions extend from the main zone toward the extension zone along a second direction the second direction that is perpendicular to the first direction. The contact regions are on ends of the line regions and are thicker than the line regions. A spacing distance in the second direction between the contact regions is greater than a spacing distance in the first direction between the line regions.Type: ApplicationFiled: May 13, 2019Publication date: September 5, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Chung-Il Hyun, Semee JANG, Sung Yun LEE
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Patent number: 10355010Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.Type: GrantFiled: October 17, 2016Date of Patent: July 16, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jang Hyun You, Jin Taek Park, Taek Soo Shin, Sung Yun Lee