Patents by Inventor Sunggil Kang

Sunggil Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990348
    Abstract: A wafer processing method includes supplying a first process gas into a wafer processing apparatus, lowering a temperature of the wafer, generating plasma using the first process gas, supplying a second process gas and mixing the second process gas with the plasma, performing a plasma process on the wafer using the plasma and the second process gas, and performing an annealing process on the wafer on which the plasma process has been performed. The lowering of the temperature of the wafer includes increasing an internal pressure of the wafer processing apparatus.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: May 21, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chanyeong Jeong, Hoseop Choi, Sunggil Kang, Dongkyu Shin, Sangjin An
  • Publication number: 20240159657
    Abstract: Provided is an apparatus configured to measure radical spatial density distribution including a process chamber including a viewport, a driving device configured to move a moving wall inside the process chamber, a light source configured to generate light, a collimator disposed in the viewport of the process chamber and configured to transmit light received from the light source to the moving wall and receive light reflected from the moving wall, and a spectrometer configured to receive the reflected light from the collimator, and measure radical spatial density based on analyzing an absorption amount of a spectrum of the received light.
    Type: Application
    Filed: May 26, 2023
    Publication date: May 16, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sejin OH, Sunggil KANG, Sangki NAM, Jeongmin BANG, Dougyong SUNG, Yeongkwang LEE, Sungho JANG, Jonghun PI
  • Patent number: 11956967
    Abstract: An integrated circuit device includes a peripheral circuit structure arranged on a substrate, a gate stack arranged on the peripheral circuit structure and including a plurality of gate electrodes, and a dam structure formed in a dam opening portion that passes through the gate stack. The dam structure includes an insulation spacer on an inner wall of the dam opening portion and a pair of sloped sidewalls at an upper side of the dam opening portion, and a buried layer filling an inside of the dam opening portion and including an air space. The integrated circuit device further includes a mold gate stack surrounded by the dam structure and including a plurality of mold layers, a plurality of conductive lines arranged on the gate stack, and a plurality of through electrodes connected to the plurality of conductive lines, passing through the mold gate stack, and surrounded by the dam structure.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: April 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunggil Kim, Kyengmun Kang, Hyeeun Hong
  • Publication number: 20240087856
    Abstract: A substrate treating apparatus includes a process chamber configured to perform plasma treatment, a substrate support in a lower portion of the process chamber and configured to support a substrate, a showerhead in an upper portion of the process chamber and configured to supply a process gas for the plasma treatment toward the substrate, and a baffle surrounding the substrate support. The substrate support functions as a first electrode for generating plasma, the showerhead and the baffle function as a second electrode for generating the plasma, the baffle has a variable height, and an area of the second electrode varies as a height of the baffle varies.
    Type: Application
    Filed: August 10, 2023
    Publication date: March 14, 2024
    Inventors: Jiwon Son, Sunggil Kang, Kangmin Do, Youngsun Kim, Younghoo Kim, Sangjin An
  • Patent number: 11798788
    Abstract: A hollow cathode includes an insulation plate having cathode holes. Bottom electrodes are below the insulation plate. The bottom electrodes define first holes having a width greater than a width of the cathode holes. Top electrodes are at an opposite side of the insulation plate from the bottom electrodes. The top electrodes define second holes aligned with the first holes along a direction orthogonal to the upper surface of the insulation plate.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: October 24, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Ki Nam, Sunggil Kang, Sungyong Lim, Beomjin Yoo, Akira Koshiishi, Vasily Pashkovskiy, Kwangyoub Heo
  • Publication number: 20230071985
    Abstract: A substrate processing apparatus includes first to fourth sets of inner surfaces that at least partially define a plasma forming region, a gas supply region, gas mixing region, and a substrate processing region, respectively, where the substrate processing apparatus is configured to form a plasma within the plasma forming region, supply a process gas from the gas supply region to the plasma forming region, form an etchant in the gas mixing region based on recombination of radicals supplied from the plasma forming region, and process a substrate based on the etchant within the substrate processing region; a shower head between the gas mixing region and the substrate processing region and configured to supply the etchant to the substrate processing region; a coating layer covering a surface of the shower head and including nickel (Ni) containing phosphorus (P); and a heater configured to control a surface temperature of the shower head.
    Type: Application
    Filed: May 20, 2022
    Publication date: March 9, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Woorim LEE, Sunggil KANG, Minhyoung KIM, Inseong KIM, Seokyoung PARK, Sangjin AN, Inhye JEONG, Kyusik CHOI
  • Publication number: 20220301827
    Abstract: A manufacturing method includes depositing a chamber protective layer in a chamber, supplying a first purge gas to the chamber, transferring a substrate to the chamber, the substrate being disposed inside an edge ring on an electrostatic chuck, processing the substrate, supplying a second purge gas to the chamber, transferring the substrate to an outside of the chamber, removing the chamber protective layer, and supplying a third purge gas to the chamber. Variation of the surface roughness of the edge ring may be minimal. A ratio of an edge gas flow rate of gas supplied to an edge of the substrate and the edge ring to a central gas flow rate of gas supplied to a central portion of the substrate in the processing the substrate may be 0.05 to 19. The flow rate ratio may be more than 1 in the supplying the second purge gas.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 22, 2022
    Inventors: Woorim LEE, Sunggil KANG, Inseong KIM, Gonjun KIM, Younghoo KIM
  • Patent number: 11289308
    Abstract: A substrate processing apparatus includes a process chamber including a plasma generation region configured to receive at least one first process gas and have first radio-frequency (RF) power applied thereto, to generate plasma; a gas distribution region configured to supply the at least one first process gas to the plasma generation region; a gas mixing region configured to receive at least one second process gas and radicals generated in the plasma generation region to generate an etchant based on the radicals being mixed with the at least one second process gas; a pedestal on which a substrate is disposed; a processing region in which the pedestal is installed; and a shower head configured to supply the etchant from the gas mixing region to the processing region, the substrate disposed on the pedestal being processed by the etchant. The gas mixing region is separate from each of the plasma generation region and the processing region.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: March 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangjin An, Minseop Park, Chanyeong Jeong, Sunggil Kang, Yeongkwang Lee
  • Publication number: 20220068659
    Abstract: A wafer processing method includes supplying a first process gas into a wafer processing apparatus, lowering a temperature of the wafer, generating plasma using the first process gas, supplying a second process gas and mixing the second process gas with the plasma, performing a plasma process on the wafer using the plasma and the second process gas, and performing an annealing process on the wafer on which the plasma process has been performed. The lowering of the temperature of the wafer includes increasing an internal pressure of the wafer processing apparatus.
    Type: Application
    Filed: February 24, 2021
    Publication date: March 3, 2022
    Inventors: CHANYEONG JEONG, HOSEOP CHOI, SUNGGIL KANG, DONGKYU SHIN, SANGJIN AN
  • Publication number: 20210098232
    Abstract: A substrate processing apparatus includes a process chamber including a plasma generation region configured to receive at least one first process gas and have first radio-frequency (RF) power applied thereto, to generate plasma; a gas distribution region configured to supply the at least one first process gas to the plasma generation region; a gas mixing region configured to receive at least one second process gas and radicals generated in the plasma generation region to generate an etchant based on the radicals being mixed with the at least one second process gas; a pedestal on which a substrate is disposed; a processing region in which the pedestal is installed; and a shower head configured to supply the etchant from the gas mixing region to the processing region, the substrate disposed on the pedestal being processed by the etchant. The gas mixing region is separate from each of the plasma generation region and the processing region.
    Type: Application
    Filed: April 28, 2020
    Publication date: April 1, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangjin AN, Minseop PARK, Chanyeong JEONG, Sunggil KANG, Yeongkwang LEE
  • Patent number: 10950414
    Abstract: Disclosed are a plasma processing apparatus and a method of manufacturing a semiconductor device using the same. The plasma processing apparatus comprises a chamber, an electrostatic chuck in the chamber and loading a substrate, a plasma electrode generating an upper plasma on the electrostatic chuck; and a hollow cathode between the plasma electrode and the electrostatic chuck, wherein the hollow cathode generates a lower plasma below the upper plasma. The hollow cathode comprises cathode holes each having a size less than a thickness of a plasma sheath of the upper plasma.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Ki Nam, Akira Koshiishi, Kwangyoub Heo, Sunggil Kang, Beomjin Yoo, Sungyong Lim, Vasily Pashkovskiy
  • Publication number: 20210057193
    Abstract: A hollow cathode includes an insulation plate having cathode holes. Bottom electrodes are below the insulation plate. The bottom electrodes define first holes having a width greater than a width of the cathode holes. Top electrodes are at an opposite side of the insulation plate from the bottom electrodes. The top electrodes define second holes aligned with the first holes along a direction orthogonal to the upper surface of the insulation plate.
    Type: Application
    Filed: November 6, 2020
    Publication date: February 25, 2021
    Inventors: SANG KI NAM, SUNGGIL KANG, SUNGYONG LIM, BEOMJIN YOO, AKIRA KOSHIISHI, VASILY PASHKOVSKIY, KWANGYOUB HEO
  • Patent number: 10522332
    Abstract: A chamber has an upper housing and a lower housing and receives a reaction gas. A first plasma source includes electron beam sources providing electron beams into the upper housing to generate an upper plasma. A second plasma source includes holes generating a lower plasma within the holes connecting the upper housing and the lower housing. Radicals of the upper plasma, radicals of the lower plasma, and ions of the lower plasma are provided, through the holes, to the lower housing so that the lower housing has radicals and ions at a predetermined ratio of the ions to the radicals in concentration. The second plasma source divides the chamber into the upper housing and the lower housing. A wafer chuck is positioned in the lower housing to receive a wafer.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeongkwang Lee, Sunggil Kang, Sang Ki Nam, Kwangyoub Heo, Kyuhee Han
  • Publication number: 20190279846
    Abstract: A chamber has an upper housing and a lower housing and receives a reaction gas. A first plasma source includes electron beam sources providing electron beams into the upper housing to generate an upper plasma. A second plasma source includes holes generating a lower plasma within the holes connecting the upper housing and the lower housing. Radicals of the upper plasma, radicals of the lower plasma, and ions of the lower plasma are provided, through the holes, to the lower housing so that the lower housing has radicals and ions at a predetermined ratio of the ions to the radicals in concentration. The second plasma source divides the chamber into the upper housing and the lower housing. A wafer chuck is positioned in the lower housing to receive a wafer.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 12, 2019
    Inventors: Yeongkwang LEE, Sunggil KANG, Sang Ki NAM, Kwangyoub HEO, Kyuhee HAN
  • Patent number: 10347468
    Abstract: A chamber has an upper housing and a lower housing and receives a reaction gas. A first plasma source includes electron beam sources providing electron beams into the upper housing to generate an upper plasma. A second plasma source includes holes generating a lower plasma within the holes connecting the upper housing and the lower housing. Radicals of the upper plasma, radicals of the lower plasma, and ions of the lower plasma are provided, through the holes, to the lower housing so that the lower housing has radicals and ions at a predetermined ratio of the ions to the radicals in concentration. The second plasma source divides the chamber into the upper housing and the lower housing. A wafer chuck is positioned in the lower housing to receive a wafer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeongkwang Lee, Sunggil Kang, Sang Ki Nam, Kwangyoub Heo, Kyuhee Han
  • Publication number: 20190122867
    Abstract: A hollow cathode includes an insulation plate having cathode holes. Bottom electrodes are below the insulation plate. The bottom electrodes define first holes having a width greater than a width of the cathode holes. Top electrodes are at an opposite side of the insulation plate from the bottom electrodes. The top electrodes define second holes aligned with the first holes along a direction orthogonal to the upper surface of the insulation plate.
    Type: Application
    Filed: May 29, 2018
    Publication date: April 25, 2019
    Inventors: Sang Ki Nam, Sunggil Kang, Sungyong Lim, Beomjin Yoo, Akira Koshiishi, Vasily Pashkovskiy, Kwangyoub Heo
  • Publication number: 20190122860
    Abstract: A chamber has an upper housing and a lower housing and receives a reaction gas. A first plasma source includes electron beam sources providing electron beams into the upper housing to generate an upper plasma. A second plasma source includes holes generating a lower plasma within the holes connecting the upper housing and the lower housing. Radicals of the upper plasma, radicals of the lower plasma, and ions of the lower plasma are provided, through the holes, to the lower housing so that the lower housing has radicals and ions at a predetermined ratio of the ions to the radicals in concentration. The second plasma source divides the chamber into the upper housing and the lower housing. A wafer chuck is positioned in the lower housing to receive a wafer.
    Type: Application
    Filed: January 12, 2018
    Publication date: April 25, 2019
    Inventors: YEONGKWANG LEE, Sunggil KANG, Sang Ki NAM, Kwangyoub HEO, KYUHEE HAN
  • Publication number: 20190122866
    Abstract: Disclosed are a plasma processing apparatus and a method of manufacturing a semiconductor device using the same. The plasma processing apparatus comprises a chamber, an electrostatic chuck in the chamber and loading a substrate, a plasma electrode generating an upper plasma on the electrostatic chuck; and a hollow cathode between the plasma electrode and the electrostatic chuck, wherein the hollow cathode generates a lower plasma below the upper plasma. The hollow cathode comprises cathode holes each having a size less than a thickness of a plasma sheath of the upper plasma.
    Type: Application
    Filed: May 18, 2018
    Publication date: April 25, 2019
    Inventors: Sang Ki Nam, Akira KOSHIISHI, Kwangyoub HEO, Sunggil KANG, Beomjin YOO, Sungyong LIM, Vasily PASHKOVSKIY
  • Publication number: 20130116682
    Abstract: The present disclosure provides a plasma system including a plasma device having at least one electrode; an ionizable media source coupled to the plasma device and configured to supply ionizable media thereto; a precursor source configured to supply at least one monomer precursor to the plasma device; and a power source coupled to the at least one electrode and configured to ignite the ionizable media at the plasma device to form a plasma effluent at atmospheric conditions, wherein the plasma effluent polymerizes the at least one monomer precursor to form a hydrophobic, electrically-conductive polymer.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 9, 2013
    Applicant: Colorado State University Research Foundation
    Inventors: IL-GYO KOO, Paul Y. Kim, Sunggil Kang, George J. Collins