HOLLOW CATHODE, AN APPARATUS INCLUDING A HOLLOW CATHODE FOR MANUFACTURING A SEMICONDUCTOR DEVICE, AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING A HOLLOW CATHODE

Abstract

A hollow cathode includes an insulation plate having cathode holes. Bottom electrodes are below the insulation plate. The bottom electrodes define first holes having a width greater than a width of the cathode holes. Top electrodes are at an opposite side of the insulation plate from the bottom electrodes. The top electrodes define second holes aligned with the first holes along a direction orthogonal to the upper surface of the insulation plate.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional patent application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2017-0137420 filed on Oct. 23, 2017, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

Exemplary embodiments of the present inventive concept relate to a hollow cathode, and more particularly to an apparatus including a hollow cathode for manufacturing a semiconductor device, and a method of manufacturing a semiconductor device using a hollow cathode.

DISCUSSION OF RELATED ART

In general, a semiconductor device may be manufactured by employing a plurality of unit processes. The unit processes may include a thin-layer deposition process, a lithography process, and an etching process. Plasma may be used to perform the thin-layer deposition process and the etching process. The plasma may treat substrates at relatively high temperatures. Relatively high frequency power is generally used to produce the plasma.

SUMMARY

An exemplary embodiment of the present inventive concept provides a hollow cathode capable of generating pixelated plasma and an apparatus for manufacturing a semiconductor device. The apparatus for manufacturing the semiconductor device is equipped with the hollow cathode.

An exemplary embodiment of the present inventive concept provides a method of manufacturing a semiconductor device. The method increases etch uniformity.

According to an exemplary embodiment of the present inventive concept, a hollow cathode includes an insulation plate having cathode holes. Bottom electrodes are below the insulation plate. The bottom electrodes define first holes having a width greater than a width of the cathode holes. Top electrodes are at an opposite side of the insulation plate from the bottom electrodes. The top electrodes define second holes aligned with the first holes along a direction orthogonal to the upper surface of the insulation plate.

According to an exemplary embodiment of the present inventive concept, an apparatus for manufacturing a semiconductor device includes a chamber and an electrostatic chuck in the chamber. A hollow cathode is in the chamber. The hollow cathode is disposed above the electrostatic chuck. The hollow cathode includes an insulation plate having cathode holes. Bottom electrodes are below the insulation plate. The bottom electrodes define first holes having a width greater than a width of the cathode holes. Top electrodes are at opposite sides of the insulation plate from the bottom electrodes. The top electrodes define second holes aligned with the first holes along a direction orthogonal to an upper surface of the insulation plate.

According to an exemplary embodiment of the present inventive concept, a method of manufacturing a semiconductor device includes obtaining a measurement of etch uniformity of a substrate by detecting a difference in etch rate depending on locations on the substrate. The method includes determining positions of bottom electrodes and top electrodes of a hollow cathode that are configured to be individually supplied with a source power and a bias power according to the detected differences in etch rate depending on locations on the substrate. The method includes locally generating a plasma on the substrate by selectively providing the source power and the bias power to the bottom electrodes and the top electrodes based on the differences in etch rate depending on locations on the substrate.

According to an exemplary embodiment of the present inventive concept, an apparatus for etching a semiconductor device includes an etching chamber and an electrostatic chuck positioned in the etching chamber. A plurality of reaction gas chambers are positioned above the etching chamber. Each of the reaction gas chambers is individually connected to a gas supply. The reaction gas chambers are separated from each other by partitions. A hollow cathode is positioned between the etching chamber and the plurality of reaction gas chambers. The hollow cathode includes a plurality of cathode holes positioned over the electrostatic chuck. The hollow cathode includes upper and lower electrodes adjacent to each cathode hole of the plurality of cathode holes. The upper and lower electrodes are disposed on an insulation plate.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof, with reference to the accompanying drawings, in which:

FIG. 1 illustrates an apparatus for manufacturing a semiconductor device according to an exemplary embodiment of the present inventive concept.

FIG. 2 is a plan view of the hollow cathode of in FIG. 1 according to an exemplary embodiment of the present inventive concept.

FIG. 3 is a cross-sectional view taken along line I-I′ of FIG. 2.

FIG. 4 is a circuit diagram of a bias power supply of FIG. 1.

FIG. 5 is a schematic diagram of an apparatus for manufacturing a semiconductor device according to an exemplary embodiment of the present inventive concept.

FIG. 6 is a plan view of a hollow cathode, a bias power supply, and a source power supply of FIG. 5 according to an exemplary embodiment of the present inventive concept.

FIG. 7 is a cross-sectional view taken along line II-II′ of FIG. 6.

FIG. 8 is a plan of a hollow cathode of FIG. 5 according to an exemplary embodiment of the present inventive concept.

FIG. 9 is a cross-sectional view taken along line III-III′ of FIG. 8.

FIG. 10 is a plan view of a shutter plate of FIG. 9 according to an exemplary embodiment of the present inventive concept.

FIG. 11 is a cross-sectional view taken along line IV-IV′ of FIG. 10.

FIG. 12 is a flow chart of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present inventive concept.

FIG. 13 is a flow chart of a substrate etching step of FIG. 12.

FIG. 14 is a plan view of a cathode of FIG. 1 according to an exemplary embodiment of the present inventive concept.

Since FIGS. 1-14 are intended for illustrative purposes, the elements in the drawings are not necessarily drawn to scale. For example, some of the elements may be enlarged or exaggerated for clarity of description.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG. 1 illustrates an apparatus for manufacturing a semiconductor device according to an exemplary embodiment of the present inventive concept.

FIG. 1 illustrates an apparatus 100 for manufacturing a semiconductor device according to an exemplary embodiment of the present inventive concept.

Referring to FIG. 1, the apparatus 100 for manufacturing a semiconductor device according to an exemplary embodiment of the present inventive concept may be or include a substrate etching apparatus or a thin-layer deposition apparatus. In an exemplary embodiment of the present inventive concept, the semiconductor device manufacturing apparatus 100 may include a chamber 10, a gas supply 20, an electrostatic chuck 30, a bias power supply 40, and a hollow cathode 50. A substrate W may be provided in the chamber 10. The substrate may be disposed on the electrostatic chuck 30. The gas supply 20 may provide a reaction gas 22 into the chamber 10. For example, the reaction gas 22 may be injected above the hollow cathode 50. The substrate W may be loaded on the electrostatic chuck 30. The bias power supply 40 may provide the hollow cathode 50 with a bias power 42. The hollow cathode 50 may use the bias power 42 to generate plasma 70 of the reaction gas 22. The substrate W may receive the plasma 70. The plasma 70 may be selectively pixelated to locally etch the substrate W. Thus, the etching rates of the substrate by the plasma 70 may vary across different locations of the substrate W. The pixelated plasma 70 will be described in more detail below.

The chamber 10 may provide the substrate W with an isolated space from the outside. Thus, the chamber may be a sealed, airtight space that is isolated from the air outside the chamber. For example, the chamber 10 may have a pressure of about 10⁻³ Torr. In an exemplary embodiment of the present inventive concept, the chamber 10 may include a lower housing 12 and an upper housing 14. The upper housing 14 may be combined onto the lower housing 12. The upper housing 14 may have partitions 16. The partitions 16 may separate the upper housing into a plurality of chambers above the hollow cathode 50. The lower housing 12 may be separated from the upper housing 14. As an example, when the lower housing 12 and the upper housing 14 are separated from each other, the substrate W may be positioned on the electrostatic chuck 30. The upper housing 14 and the lower housing 12 may be combined to each other (e.g., after the substrate W is positioned on the electrostatic chuck 30).

The gas supply 20 may be connected with the upper housing 14. The gas supply 20 may supply the reaction gas 22 to flow between the partitions 16 of the upper housing 14. The plasma 70 may be generated between the partitions 16 (e.g., in the cathode holes 60). The partitions 16 may separate the plasma 70 formed in cathode holes 60 that are spaced apart from each other. The reaction gas 22 may include an etching gas (e.g., SF₆, HF, HCl, HBr, or CH₄) of the substrate W, an inert gas (e.g., Ar or He), or a purge gas (e.g., N₂) (e.g., when the semiconductor device manufacturing apparatus 100 is a substrate etching apparatus). Alternatively, the reaction gas 22 may include a deposition gas (e.g., SiH₄, NO, O₂, or NH₃) (e.g., when the semiconductor device manufacturing apparatus 100 is a thin-layer deposition apparatus).

The electrostatic chuck 30 may be positioned in the lower housing 12. The electrostatic chuck 30 may use an electrostatic force to hold the substrate W. The electrostatic chuck 30 may have a plasma electrode that concentrates the plasma 70 onto the substrate W.

The bias power supply 40 may be positioned outside the chamber 10. The bias power supply 40 may be connected to the hollow cathode 50. The bias power 42 produced from the bias power supply 40 may control intensity of the plasma 70. When the bias power 42 rises, the intensity of the plasma 70 may increase.

The hollow cathode 50 may be disposed in the upper housing 14. Alternatively, the hollow cathode 50 may be disposed in the lower housing 12. The hollow cathode 50 may extend along a direction parallel to an extending direction of the electrostatic chuck 30 and/or the substrate W (e.g., a first direction D1). The hollow cathode 50 may have a thickness greater than that of the electrostatic chuck 30 and/or that of the substrate W (e.g., along a direction perpendicular to the first direction, such as, for example, a third direction D3).

FIG. 2 is a plan view of the hollow cathode of in FIG. 1 according to an exemplary embodiment of the present inventive concept. FIG. 3 is a cross-sectional view taken along line I-I′ of FIG. 2.

FIG. 2 illustrates an example of a hollow cathode 50 of FIG. 1. FIG. 3 is a cross-sectional view taken along line I-I′ of FIG. 2.

Referring to FIGS. 2 and 3, the hollow cathode 50 may include an insulation plate 52, bottom electrodes 54, top electrodes 56, upper electrical lines 57, an upper protection layer 58, and a lower protection layer 59.

The insulation plate 52 may be a circular disc including a ceramic dielectric (e.g. Al₂O₃, Y₂O₃). The insulation plate 52 may have cathode holes 60. The cathode holes 60 may allow the reaction gas 22 on the insulation plate 52 to pass through toward the substrate W. For example, the reaction gas may pass from a region of the upper housing 14 toward a region of the lower housing 12 (e.g., between the partitions 16). The plasma 70 may be generated in the cathode holes 60. The plasma 70 may etch the substrate W. Each of the cathode holes 60 may have substantially a same width as that of a plasma sheath (e.g., along the first direction D1). For example, each of the cathode holes 60 may have a width (e.g., a diameter) of about 0.5 mm.

The bottom electrodes 54 may be disposed below or on the insulation plate 52. Each of the bottom electrodes 54 may have a bar shape (e.g., a rectangular shape) extending in the first direction D1. The bottom electrodes 54 may be spaced apart from each other in a second direction D2. The second direction D2 may be perpendicular to the first direction D1. Thus, the third direction D3 may be orthogonal to the first and second direction D1 and D2. Alternatively, the bottom electrodes 54 may be separated from each other in the first and second directions D1 and D2, thus forming a matrix or grid shape. As an example, the bottom electrodes 54 may each be electrically grounded. The bottom electrodes 54 may define first holes 62. The first holes 62 may be aligned with the cathode holes 60 (e.g., along the third direction D3). The first holes 62 may be larger than the cathode holes 60 (e.g., the first holes 62 may be wider than the cathode holes 60 in the first direction D1). The cathode holes 60 may overlap the first holes 62, when viewed in a plan view (e.g., along the third direction D3).

The top electrodes 56 may be disposed above or on the insulation plate 52. For example, the top electrode 56 may be in direct contact with an upper surface of the insulation plate 52. The top electrodes 56 may overlap (e.g., may be aligned with) the bottom electrodes 54 along the third direction D3. The top electrodes 56 may be separated from each other in the first and second directions D1 and D2, thus forming a matrix or grid shape. Each of the top electrodes 56 may have a rectangular island shape. The top electrodes 56 may have second holes 64. The second holes 64 may be positioned between adjacent top electrodes 56. The second holes 64 may overlap the first holes 62 (e.g., may be aligned with) the first holes 62 along the third direction D3.

The upper electrical lines 57 may connect the top electrodes 56 to the bias power supply 40 (see, e.g., FIG. 1). When the bottom electrodes 54 are electrically grounded, the bias power supply 40 may individually provide the bias power 42 through the upper electrical lines 57 to each of the top electrodes 56. Thus, a bias power 42 may be individually provided to each of the top electrodes 56. For example, only one top electrode of the top electrodes 56 might receive the bias power 42, or less than all top electrodes of the top electrodes 56 may receive the bias power 42. The upper electrical lines 57 may be disposed between the top electrodes 56, when viewed in a plan view (e.g., when viewed along the third direction D3).

The upper protection layer 58 may cover the top electrodes 56, the upper electrical lines 57, and the insulation plate 52. The upper protection layer 58 may protect the top electrodes 56 and the upper electrical lines 57 from the reaction gas 22. The upper protection layer 58 may include a ceramic dielectric (e.g. Al₂O₃, Y₂O₃) or silicon oxide.

The lower protection layer 59 may cover the bottom electrodes 54 and the insulation plate 52. The lower protection layer 59 may protect the bottom electrodes 54 from the reaction gas 22. The lower protection layer 59 may include a ceramic dielectric (e.g. Al₂O₃, Y₂O₃) or silicon oxide. When the insulation plate 52 includes the upper protection layer 58 and the lower protection layer 59, the insulation plate 52 may be provided therein with the bottom electrodes 54, the top electrodes 56, and the upper electrical lines 57.

FIG. 4 is a circuit diagram of a bias power supply of FIG. 1 according to an exemplary embodiment of the present inventive concept.

FIG. 4 illustrates an example of the bias power supply 40 of FIG. 1.

Referring to FIGS. 2 and 4, in an exemplary embodiment of the present inventive concept, the bias power supply 40 may include a bias power source 44, switching elements 46, and a bias driver 48. The bias power source 44 may produce the bias power 42. The switching elements 46 may be connected between the bias power source 44 and the top electrodes 56 of the hollow cathode 50. Each of the switching elements 46 may include at least one switch. The at least one switch may be disposed between the bias power source 44 and the top electrodes 56. The at least one switch may be configured to individually turn on and/or off a bias power provided to at least one top electrode of the top electrodes 56. The upper electrical lines 57 may connect the top electrodes 56 to the switching elements 46. The bias driver 48 may be individually connected to the switching elements 46. The bias driver 48 may produce turn-on signals of the switching elements 46. In response to the turn-on signals, the switching elements 46 may control the bias power 42 applied to the top electrodes 56. When the bottom electrodes 54 are electrically grounded, the bias power supply 40 may individually provide the bias power 42 to the top electrodes 56.

FIG. 5 is a schematic diagram of an apparatus for manufacturing a semiconductor device according to an exemplary embodiment of the present inventive concept.

FIG. 5 is an example of an apparatus for manufacturing a semiconductor device according to an exemplary embodiment of the present inventive concept. Like reference numerals may refer to like elements throughout the specification and drawings. Descriptions of components illustrated in FIG. 5 that are the same or substantially the same as those described above with reference to FIGS. 1 to 3 may be omitted below.

Referring to FIG. 5, an apparatus 100 for manufacturing a semiconductor device may include a source power supply 80. The source power supply 80 may provide the hollow cathode 50 with a source power 82. The source power 82 may have voltage polarity opposite to that of the bias power 42. For example, when the bias power 42 has a positive voltage, the source power 82 may have a negative voltage. When the bias power 42 and the source power 82 are applied, the plasma 70 may be generated in the cathode holes 60 of the hollow cathode 50. The plasma 70 may etch the substrate W.

FIG. 6 is a plan view of a hollow cathode, a bias power supply, and a source power supply of FIG. 5 according to an exemplary embodiment of the present inventive concept. FIG. 7 is a cross-sectional view taken along line II-II′ of FIG. 6.

FIG. 6 illustrates an example of the hollow cathode 50, the bias power supply 40, and the source power supply 80 of FIG. 5. FIG. 7 is a cross-sectional view taken along line II-II′ of FIG. 6.

Referring to FIGS. 6 and 7, each of the bottom electrodes 54 of the hollow cathode 50 may have a bar shape (e.g., a rectangular shape) extending in the first direction D1. Each of the bottom electrodes 54 may be connected with the source power supply 80. The source power supply 80 may sequentially and/or individually provide the source power 82 to the bottom electrodes 54.

Each of the top electrodes 56 may have a bar shape (e.g., a rectangular shape) extending in the second direction D2. Each of the top electrodes 56 may be connected with the bias power supply 40. The top electrodes 56 may be separated from each other in the first direction D1. The bias power supply 40 may sequentially and/or individually provide the bias power 42 to the top electrodes 56. The cathodes holes 60 and the first and second holes 62 and 64 may be located at intersections 66 between the bottom electrodes 54 and the top electrodes 56.

When the bias power 42 and the source power 82 match each other, the plasma 70 may be generated in the cathode holes 60. For example referring to FIG. 6, when the source power 82 having a voltage of about −1 V is applied to the bottom electrode 54 located first from the bottom, and when the bias power 42 having a voltage of about 1 V is applied to the top electrodes 56 located second and fourth from the left, the plasma 70 may be generated in the cathode holes 60 at the intersections 66. The positional information of the intersections 66 at which the plasma 70 is generated may be expressed by coordinate values in which a relative position of a column is expressed as a numerical value starting with “1” on the left and moving right, and a relative position of a row is expressed as a numerical value starting with “1” on the bottom and moving up. For example, referring to FIG. 6, the coordinate values of the intersections 66 at which the plasma 70 is generated may be expressed as coordinate values (2, 1) and (4, 1). Thus, an etch rate of the substrate W may be increased at the coordinate values (2, 1) and (4, 1) where the plasma 70 is generated. Thus, the hollow cathode 50 may be used to locally and selectively etch a substrate in a pinpoint manner (e.g., in a pixelated manner) according to which intersections 66 at which plasma 70 is generated.

FIG. 8 is a plan of a hollow cathode of FIG. 5 according to an exemplary embodiment of the present inventive concept. FIG. 9 is a cross-sectional view taken along line III-III′ of FIG. 8.

FIG. 8 illustrates an example of the hollow cathode 50 of FIG. 5. FIG. 9 is a cross-sectional view taken along line III-III′ of FIG. 8.

Referring to FIGS. 8 and 9, the hollow cathode 50 may include a shutter plate 90 in the insulation plate 52. Descriptions of components illustrated in FIGS. 8 and 9 that are the same or substantially the same as those described above with reference to FIGS. 3 to 7 may be omitted below.

The insulation plate 52 may have a gap 53. The gap 53 may be disposed between the bottom electrodes 54 and the top electrodes 56. The gap 53 may extend in a direction intersecting extending directions of the cathode holes 60. For example, the gap 53 may extend in the first direction D1. For example, when the cathode holes 60 extend in the third direction D3, the gap 53 may extend either in the first direction D1 or in the second direction D2.

The shutter plate 90 may be positioned in the gap 53. The shutter plate 90 may have shutter holes 92. The shutter holes 92 may be aligned with the cathode holes 60 (e.g., along the third direction D3). The shutter plate 90 may move or be moveable in the gap 53. For example, the shutter plate 90 may be moveable along the first direction D1 to move along the extending direction of the gap 53. Movement of the shutter plate 90 may open and close the cathode holes 60 by moving the shutter holes 92 into and out of alignment (e.g., along the third direction D3) with the cathode holes 60.

When the source power 82 and the bias power 42 are provided to the bottom electrodes 54 and the top electrodes 56, the plasma 70 may be generated in the cathode holes 60 and the shutter holes 92. For example, the plasma 70 may be generated in the cathode holes 60 and the shutter holes 92 when the cathode holes 60 and the shutter holes 92 are aligned (e.g., along the third direction D3).

FIG. 10 is a plan view of a shutter plate of FIG. 9 according to an exemplary embodiment of the present inventive concept. FIG. 11 is a cross-sectional view taken along line IV-IV′ of FIG. 10.

FIG. 10 illustrates an example of the shutter plate 90 that blocks the cathode holes 60 of FIG. 9. FIG. 11 is a cross-sectional view taken along line IV-IV′ of FIG. 10.

Referring to FIGS. 1, 10, and 11, the shutter plate 90 may rotate in a direction of azimuth angle θ on a plane defined by the first direction D1 and the second direction D2, thus blocking the cathode holes 60. Thus, the reaction gas 22 does not pass through the cathodes holes 60 when the cathode holes 60 are blocked by the shutter plate 90. Even when the source power 82 and the bias power 42 are provided to the bottom electrodes 54 and the top electrodes 56, the plasma 70 is not generated in the cathode holes 60 when the cathode holes 60 are blocked by the shutter plate 90.

A method of manufacturing a semiconductor device using the semiconductor device manufacturing apparatus 100, as described herein, is described in more detail below.

FIG. 12 is a flow chart of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present inventive concept.

Referring to FIG. 12, a method of manufacturing a semiconductor device may include providing bottom electrodes and top electrodes with source power and bias power (step S10). For example, the method may include providing the source power 82 and the bias power 42 to the bottom electrodes 54 and the top electrodes 56. The method may include obtaining a difference in etch rate depending on locations in the substrate (step S20). For example, the method may include obtaining etch uniformity depending on locations in the substrate W. The method may include determining locations of bottom electrodes and top electrodes that are supposed to be supplied with source power and bias power according to etch uniformity (step S30). For example, the method may include determining locations of the bottom electrodes 54 and the top electrodes 56 that are supposed to be supplied with the source power 82 and the bias power 42 according to the etch uniformity. The method may include selectively providing source power and bias power to bottom electrodes and top electrodes positioned on locations having a difference in etch rate (step S40). For example, the method may include selectively providing the source power 82 and the bias power 42 to the bottom electrodes 54 and the top electrodes 56.

The source power supply 80 and the bias power supply 40 may provide the source power 82 and the bias power 42 to the bottom electrodes 54 and the top electrodes 56, thus etching the substrate W (e.g., in step S10). The bias power 42 and the source power 82 may generate the plasma 70 in all of the cathode holes 60. The plasma 70 may etch an entire top surface of the substrate W. Alternatively, the plasma 70 may deposit a thin layer on the substrate W. For example, as described herein, plasma 70 may be generated in less than all of the cathode holes 60 to generate the plasma 70 selectively in some of the cathode holes 60 to selectively etch the substrate W.

FIG. 13 is a flow chart of a substrate etching step of FIG. 12 according to an exemplary embodiment of the present inventive concept.

FIG. 13 is an example of the substrate etching step S10 of FIG. 12.

Referring to FIG. 13, step S10 may include etching the substrate W. For example, in step S1, etching the substrate W may include providing a reaction gas to top electrodes (step S12). For example, step S12 may include supplying the reaction gas 22 onto the top electrodes 56. Step S10 may include aligning shutter holes with cathode holes (step S14). For example, step S14 may include aligning the shutter holes 92 with the cathode holes 60, and generating plasma (step S16). Thus, step S16 may include generating the plasma 70.

The gas supply 20 may supply the reaction gas 22 onto the top electrodes 56 (e.g., in step S12). The upper housing 14 may be filled with the reaction gas 22.

A controller and/or human operator may rotate the shutter plate 90 to align the shutter holes 92 with the cathode holes 60 (e.g., in step S14). The reaction gas 22 may be provided into the cathodes holes 60 and the shutter holes 92.

The source power supply 80 and the bias power supply 40 may provide the source power 82 and the bias power 42 to the bottom electrodes 54 and the top electrodes 56, and thus the plasma 70 may be generated in (e.g., in some of or in all of) the cathode holes 60 (e.g., in step S16). The plasma 70 may produce ions (e.g., H+, F+) and/or free radicals (e.g., H, F, Cl., CH₃.). The ions and free radicals of the reaction gas 22 may etch the substrate W.

Referring to FIG. 12, when the etching of the substrate W is complete, an inspection apparatus may inspect the substrate W to obtain the etch uniformity of the substrate W (e.g., in step S20). The etch uniformity may include a difference in etch rate based on locations in the substrate W.

The controller may determine the bottom electrodes 54 and the top electrodes 56 that are supposed to be supplied with the source power 82 and the bias power 42 on the basis of the etch uniformity (e.g., in step S30). The controller may compare coordinate values indicating positional information about portions of the substrate W to coordinate values in the hollow cathode 50. When coordinate values are given to indicate positional information about specific portions of the substrate W that have an etch rate less than an average etch rate of the substrate W, the controller may obtain coordinate values indicating positional information about the intersections 66 of the hollow cathode 50 that correspond to the coordinate values indicating the specific portions of the substrate W. The controller may choose the bottom and top electrodes 54 and 56 crossing at the intersections 66 at which etch values were less than average. Accordingly, the controller may determine the bottom electrodes 54 and the top electrodes 56 that are supposed to be supplied with the source power 82 and the bias power 42. Alternatively, the controller may obtain intensities of the source power 82 and the bias power 42 according to the difference in etch rate. When a particular portion of the substrate W is etched less than the average etch rate, the controller may increase the intensities of the source power 82 and the bias power 42. In contrast, when a particular portion of the substrate W is etched more than the average etch rate, the controller may decrease the intensities of the source power 82 and the bias power 42. Thus, the hollow cathode 50 may be used to locally and selectively etch a substrate in a pinpoint manner (e.g., in a pixelated manner) by increasing and decreasing etch rates of the substrate W according to which intersections 66 at which plasma 70 is generated.

The source power supply 80 and the bias power supply 40 may selectively provide the source power 82 and the bias power 42 to the bottom electrodes 54 and the top electrodes 56 expressed by coordinate values having the difference in etch rate (e.g., in step S40). For example, the plasma 70 may etch portions of the substrate W that have a relatively low etch rate (e.g., an etch rate that is less than an average etch rate). Accordingly, the etching uniformity of the substrate W may be increased. In an exemplary embodiment of the present inventive concept, the semiconductor device manufacturing apparatus 100 may include a plasma CVD apparatus. The semiconductor device manufacturing apparatus 100 may use the plasma 70 to increase deposition uniformity of thin layers.

FIG. 14 is a plan view of a cathode of FIG. 1 according to an exemplary embodiment of the present inventive concept.

FIG. 14 is an example of the hollow cathode 50 of FIG. 1.

Referring to FIGS. 3 and 14, the hollow cathode 50 may include a plate-shaped (e.g., a circular plate-shaped) bottom electrode 54 and concentric ring-shaped top electrodes 56. The insulation plate 52 may be substantially the same as the insulation plate 52 described above with reference to FIG. 2.

The bottom electrode 54 may cover (e.g., may overlap along the third direction D3) substantially the entire top surface of the substrate W. The top electrodes 56 may be separated from each other. For example, the top electrodes 56 may be separated from each other in a radius direction of the substrate W, and may be connected to the upper electrical lines 57. In an exemplary embodiment of the present inventive concept, the top electrodes 56 may include a central ring 82, a middle ring 84, and an edge ring 86.

The central ring 82 may be disposed inside the middle ring 84 (e.g., when viewed in a plan view along the third direction D3). The central ring 82 may overlap a central region of the substrate W (e.g., when viewed in a plan view along the third direction D3). When the central ring 82 is provided with the bias power (e.g., bias power 42 described above), the plasma 70 may be generated in the cathode holes 60 provided in the central ring 82. The plasma 70 may selectively and/or locally etch the central region of the substrate W.

The middle ring 84 may be provided between the central ring 82 and the edge ring 86. The middle ring 84 may be disposed on a middle region between central and edge regions of the substrate W. When the middle ring 84 is provided with the bias power 42, the plasma 70 may be generated in the cathode holes 60 provided in the middle ring 84. The plasma 70 may selectively and/or locally etch the middle region of the substrate W.

The edge ring 86 may surround the middle ring 84. The edge ring 86 may be disposed on the edge region of the substrate W. When the edge ring 86 is provided with the bias power 42, the plasma 70 may be generated in the cathode holes 60 provided in the edge ring 86. The plasma 70 may selectively and/or locally etch the edge region of the substrate W. Thus, the hollow cathode 50 may be used to locally and selectively etch a substrate in a pinpoint manner (e.g., in a pixelated manner) by increasing and decreasing etch rates of the substrate W according to which intersections 66 at which plasma 70 is generated.

As discussed above, a difference in intensity of the bias power 42 may be opposite to the difference in etch rate of the substrate W. For example, when the central region has an etch rate greater than that of the edge region, the intensity of the bias power 42 applied to the central ring 82 may be less than the intensity of the bias power 42 applied to the edge ring 86.

According to an exemplary embodiment of the present inventive concept, an apparatus for etching a semiconductor device may include an etching chamber (see, e.g., lower housing 12 of chamber 10 in FIG. 1) and the electrostatic chuck 30 positioned in the etching chamber. A plurality of reaction gas chambers (see, e.g., upper housing 14 of chamber 10 in FIG. 1 including partitions 16) may be positioned above the etching chamber. Each of the reaction gas chambers may be individually connected to the gas supply 20. The reaction gas chambers may be separated from each other by partitions 16. The hollow cathode 50 may be positioned between the etching chamber and the plurality of reaction gas chambers. The hollow cathode 50 may include a plurality of cathode holes 60 positioned over the electrostatic chuck 30. The hollow cathode 50 may include upper and lower electrodes (e.g., 54 and 56) adjacent to each cathode hole of the plurality of cathode holes 60. The upper and lower electrodes may be disposed on the insulation plate 52. A reaction gas may be individually supplied to each of the reaction gas chambers. Thus, reaction gas chambers positioned above upper and lower electrodes which are not provided with a bias and/or a source power (as described above in more detail) might not be supplied with reaction gas 22. Thus, an amount of reaction gas 22 used may be reduced, manufacturing costs may be reduced and efficiency of semiconductor manufacturing (e.g., etching) may be increased.

An apparatus for manufacturing a semiconductor device according to an exemplary embodiment of the present inventive concept may include the bottom and top electrodes intersecting at the cathode holes of the insulation plate. The bottom electrodes and the top electrodes may use the source power and the bias power to generate the pixelated plasma in the cathode holes. The pixelated plasma may locally etch the substrate, thus increasing etch uniformity of a substrate.

While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept.

Claims

1. A hollow cathode, comprising:

an insulation plate having cathode holes;

bottom electrodes below the insulation plate, wherein the bottom electrodes define first holes having a width greater than a width of the cathode holes; and

top electrodes at an opposite side of the insulation plate from the bottom electrodes and defining second holes aligned with the first holes along a direction orthogonal to an upper surface of the insulation plate.

2. The hollow cathode of claim 1, wherein each of the bottom electrodes extends in a first direction,

wherein the top electrodes overlap the bottom electrodes along the direction orthogonal to the upper surface of the insulation plate, and

wherein the top electrodes are separated from each other in the first direction and in a second direction intersecting the first direction.

3. The hollow cathode of claim 2, further comprising upper electrical lines above the insulation plate, wherein each upper electrical line of the upper electrical lines is individually connected to a top electrode of the top electrodes.

4. The hollow cathode of claim 1, wherein the bottom electrodes extend in a first direction,

wherein the top electrodes extend in a second direction intersecting the first direction, and

wherein the cathode holes and the first and second holes are disposed at intersections between the bottom electrodes and the top electrodes.

5. The hollow cathode of claim 4, wherein the insulation plate has a gap between the top electrodes and the bottom electrodes.

6. The hollow cathode of claim 5, further comprising a shutter plate in the gap.

7. The hollow cathode of claim 6, wherein the shutter plate has shutter holes aligned with the cathode holes along the direction orthogonal to the upper surface of the insulation plate.

8. The hollow cathode of claim 1, wherein the top electrodes each comprise:

an edge ring;

a central ring in the edge ring; and

a middle ring between the central ring and the edge ring.

9. The hollow cathode of claim 1, wherein the insulation plate comprises a ceramic dielectric.

10. The hollow cathode of claim 1, further comprising:

an upper protection layer disposed on the top electrodes and the insulation plate; and

a lower protection layer disposed on the bottom electrodes and the insulation plate.

11. An apparatus for manufacturing a semiconductor device, the apparatus comprising:

a chamber;

an electrostatic chuck in the chamber; and

a hollow cathode in the chamber, the hollow cathode being disposed above the electrostatic chuck,

wherein the hollow cathode comprises: an insulation plate having cathode holes; bottom electrodes below the insulation plate, wherein the bottom electrodes define first holes having a width greater than a width of the cathode holes; and top electrodes at an opposite side of the insulation plate from the bottom electrodes and defining second holes aligned with the first holes along a direction orthogonal to an upper surface of the insulation plate.

12. The apparatus of claim 11, further comprising a bias power supply configured to provide a bias power to the top electrodes,

wherein the bias power supply comprises:

a bias power source;

switches connected between the bias power source and the top electrodes, the switches each controlling a flow of the bias power to a top electrode of the top electrodes; and

a bias power driver turning on the switches to individually provide the bias power to the top electrode of the top electrodes.

13. The apparatus of claim 12, further comprising a source power supply configured to provide a source power to the bottom electrodes,

wherein the source power has voltage polarity opposite to that of the bias power.

14. The apparatus of claim 11, wherein the chamber comprises:

a lower housing; and

an upper housing on the lower housing,

wherein the hollow cathode is disposed in the upper housing.

15. The apparatus of claim 14, wherein the upper housing has partitions between the cathode holes.

16-20. (canceled)

21. An apparatus for etching a semiconductor device, comprising:

an etching chamber;

an electrostatic chuck positioned in the etching chamber;

a plurality of reaction gas chambers positioned above the etching chamber, wherein each of the reaction gas chambers is individually connected to a gas supply, and wherein the reaction gas chambers are separated from each other by partitions; and

a hollow cathode positioned between the etching chamber and the plurality of reaction gas chambers,

wherein the hollow cathode comprises a plurality of cathode holes positioned over the electrostatic chuck, and

wherein the hollow cathode comprise upper and lower electrodes adjacent to each cathode hole of the plurality of cathode holes, wherein the upper and lower electrodes are disposed on an insulation plate.