Abstract: A display device includes: a substrate; a spacer on the substrate and including: an upper surface; a first side surface extending toward the substrate from a first end of the upper surface; and a second side surface extending toward the substrate from a second end of the upper surface; an active pattern on the first side surface of the spacer, including a metal oxide semiconductor, and having a source region and a drain region; a source electrode on the second side surface of the spacer and the active pattern, and connected to the source region; a drain electrode on the substrate, including a same material as the source electrode, and connected to the drain region; and a first gate electrode on the active pattern and partially overlapping the first side surface of the spacer.

Abstract: A display device is provided. The display device includes a substrate including first and second pixel areas that are adjacent. The display device includes a via layer on the substrate defining first and second grooves overlapping the first and second pixel areas, respectively, and a depth of the first groove that is different from a depth of the second groove. The display device includes first and second pixel electrodes in the first and second grooves, respectively, the levels of upper surfaces of the pixel electrodes are higher than a level of any upper surface of the via layer and the thicknesses of the pixel electrodes are different. The display device includes a light emitting layer on the pixel electrodes.

Abstract: A gate driving circuit includes a stage configured to output a scan gate signal based on a scan clock signal, a voltage of a first node, and a voltage of a second node, and to output a sensing gate signal based on, a sensing clock signal, the voltage of the first node, and the voltage of the second node. The stage includes: a first sensing circuit configured to select a gate line to be sensed based on a S1 signal or to determine a frame reset based on a S7 signal; a first inverting circuit configured to control the first sensing circuit base on the S7 signal; and a second sensing circuit configured to control the voltage of the first node using the first sensing circuit based on a S2 signal. The frame reset is determined based on a maximum frequency of a variable frame frequency.

Abstract: A display device includes a via-insulating layer defining a trench including a substantially inclined surface and a substantially flat surface, a light emitting layer on the via-insulating layer and including a first portion parallel to the substantially inclined surface and a second portion disposed parallel to the substantially flat surface, and a color conversion layer on the light emitting layer. A first angle formed between a first imaginary straight line, which connects a point where the first portion and the second portion meet and an edge of the color conversion layer and forms an obtuse angle with the first portion, and a second imaginary straight line, which extends perpendicular to the first portion, is greater than a second angle formed between a travel direction of a light having a greatest luminous intensity among lights emitted from the first portion and the second imaginary straight line.

Abstract: A gate driving circuit includes a stage configured to output a scan gate signal based on a scan clock signal, a voltage of a first node, and a voltage of a second node, and to output a sensing gate signal based on, a sensing clock signal, the voltage of the first node, and the voltage of the second node. The stage includes: a first sensing circuit configured to select a gate line to be sensed based on a S1 signal or to determine a frame reset based on a S7 signal; a first inverting circuit configured to control the first sensing circuit base on the S7 signal; and a second sensing circuit configured to control the voltage of the first node using the first sensing circuit based on a S2 signal. The frame reset is determined based on a maximum frequency of a variable frame frequency.

Abstract: A display device includes: a substrate; a spacer on the substrate and including: an upper surface; a first side surface extending toward the substrate from a first end of the upper surface; and a second side surface extending toward the substrate from a second end of the upper surface; an active pattern on the first side surface of the spacer, including a metal oxide semiconductor, and having a source region and a drain region; a source electrode on the second side surface of the spacer and the active pattern, and connected to the source region; a drain electrode on the substrate, including a same material as the source electrode, and connected to the drain region; and a first gate electrode on the active pattern and partially overlapping the first side surface of the spacer.

Abstract: A gate driving circuit includes a plurality of unit stages connected to each other, wherein each of the plurality of unit stages includes a first transistor having a lower gate electrode, an upper gate electrode disposed on the lower gate electrode, an active layer disposed between the lower gate electrode and the upper gate electrode, a first electrode contacting a first portion of the active layer, and a second electrode contacting a second portion of the active layer, a first capacitor defined by a first region in which the lower gate electrode and the upper gate electrode overlap, and a second capacitor defined by a second region in which the upper gate electrode and the first electrode overlap, wherein the upper gate electrode and the lower gate electrode are electrically coupled to each other in the first region where the upper gate electrode and the lower gate electrode overlap to form the first capacitor.

Abstract: An organic light emitting diode display device includes a substrate, an active layer disposed on the substrate and including a metal oxide-based semiconductor, a gate electrode disposed on the active layer, an insulating layer disposed on the gate electrode, source and drain electrodes disposed on the insulating layer, a light emitting element on the source and drain electrodes, and a gate insulating layer between the active layer and the gate electrode. The gate insulating layer includes first and second gate insulating layers. The first gate insulating layer directly contacts the active layer and has a first amount of nitrogen. The second gate insulating layer is disposed on the first gate insulating layer and has a second amount of nitrogen that is different from the first amount of nitrogen.

Abstract: A gate driving circuit includes a plurality of unit stages connected to each other, wherein each of the plurality of unit stages includes a first transistor having a lower gate electrode, an upper gate electrode disposed on the lower gate electrode, an active layer disposed between the lower gate electrode and the upper gate electrode, a first electrode contacting a first portion of the active layer, and a second electrode contacting a second portion of the active layer, a first capacitor defined by a first region in which the lower gate electrode and the upper gate electrode overlap, and a second capacitor defined by a second region in which the upper gate electrode and the first electrode overlap, wherein the upper gate electrode and the lower gate electrode are electrically coupled to each other in the first region where the upper gate electrode and the lower gate electrode overlap to form the first capacitor.

Abstract: A leadtab assembly may include an electrode non-coating portion having a plurality of stacked electrodes collected inside a battery cell, a leadtab for forming an electrical path to the outside of the battery cell, and a bonding portion for mutually bonding the electrode non-coating portion and the leadtab, wherein a cutting prevention portion is elastically deformed by the force applied to the electrode non-coating portion as the electrode is expanded at the bonding point located between the bonding portion and the leadtab.

Abstract: An organic light emitting diode display device includes a substrate, an active layer disposed on the substrate and including a metal oxide-based semiconductor, a gate electrode disposed on the active layer, an insulating layer disposed on the gate electrode, source and drain electrodes disposed on the insulating layer, a light emitting element on the source and drain electrodes, and a gate insulating layer between the active layer and the gate electrode. The gate insulating layer includes first and second gate insulating layers. The first gate insulating layer directly contacts the active layer and has a first amount of nitrogen. The second gate insulating layer is disposed on the first gate insulating layer and has a second amount of nitrogen that is different from the first amount of nitrogen.

Abstract: A leadtab assembly may include an electrode non-coating portion having a plurality of stacked electrodes collected inside a battery cell, a leadtab for forming an electrical path to the outside of the battery cell, and a bonding portion for mutually bonding the electrode non-coating portion and the leadtab, wherein a cutting prevention portion is elastically deformed by the force applied to the electrode non-coating portion as the electrode is expanded at the bonding point located between the bonding portion and the leadtab.

Abstract: A wireless multi-hop network includes a source node, at least one relay node, and a destination node. Each relay node is configured to perform partial decoding on a received signal including at least one previous-hop transmission signal according to a predefined function to calculate a function signal for the at least one previous-hop transmission signal, and encode the function signal and transmit the encoded function signal to a next hop. A destination node includes a receiver configured to obtain a received signal comprising a combination of a plurality of transmission signals for transmission by a source node and to be relayed by at least one relay node, and a decoder configured to configure a decoder graph corresponding to channel coding by the source node and relay nodes and to joint-decode the received signal according to the decoder graph to detect information blocks from the received signal.

Abstract: An image forming apparatus includes a phase controller for controlling input power applied to a heating body through phase control. The image forming apparatus includes a fuser having the heating body, a switching unit supplying the input power to the heating body, and a phase controller determining an input phase of the input power based on a temperature of the fuser, in which the phase controller further controls the switching unit to vary a phase of the input power supplied to the heating body within a phase range set based on the input phase, for each control cycle of the input power.

Abstract: A liquid crystal display includes a substrate, a plurality of signal lines, a gate driver, and a sealant. The substrate includes a display area and a peripheral area outside the display area. The signal lines are integrated with the substrate and include a clock signal line. The gate driver includes a stage located between the clock signal line and the display area. The stage is integrated with the substrate and is configured to apply a gate voltage to the display area. The sealant is distributed over part of the peripheral area. A seal region where the sealant is distributed includes a seal line, and the clock signal line is located within the seal line. The clock signal line is located further away from the stage than the other signal lines.

Abstract: A thin film transistor array panel includes: a data line which extends in a column direction and transfers a data voltage; a first pixel electrode and a second pixel electrode connected to the data line and adjacent in a row direction; a first thin film transistor connected to the first pixel electrode and the data line, and including a first source electrode and a first drain electrode; and a second thin film transistor connected to the second pixel electrode and the data line, and including a second source electrode and a second drain electrode. The first pixel electrode is at the right of the data line, the second pixel electrode is at the left of the data line, and relative positions of the first source electrode and the first drain electrode are the same as relative positions of the second source electrode and the second drain electrode.

Abstract: A liquid crystal display includes: a first insulation substrate; a first gate conductor disposed on the first insulation substrate and in a same layer as a gate line and a second gate conductor disposed on the first insulation substrate and in the same layer as the gate line; a gate insulating layer disposed on the first gate conductor and the second gate conductor; a data conductor disposed on the gate insulating layer and in a same layer as a data line; a thin film transistor disposed on the first insulation substrate; a first spacer disposed on the first insulation substrate; and a second spacer disposed on the first insulation substrate, where heights or widths of the first and second spacers are different from each other and having different heights or widths, and the second spacer overlaps the first gate conductor and the second gate conductor.

Abstract: A liquid crystal display includes a substrate, a plurality of signal lines, a gate driver, and a sealant. The substrate includes a display area and a peripheral area outside the display area. The signal lines are integrated with the substrate and include a clock signal line. The gate driver includes a stage located between the clock signal line and the display area. The stage is integrated with the substrate and is configured to apply a gate voltage to the display area. The sealant is distributed over part of the peripheral area. A seal region where the sealant is distributed includes a seal line, and the clock signal line is located within the seal line. The clock signal line is located further away from the stage than the other signal lines.

Abstract: An image forming apparatus includes a phase controller for controlling input power applied to a heating body through phase control. The image forming apparatus includes a fuser having the heating body, a switching unit supplying the input power to the heating body, and a phase controller determining an input phase of the input power based on a temperature of the fuser, in which the phase controller further controls the switching unit to vary a phase of the input power supplied to the heating body within a phase range set based on the input phase, for each control cycle of the input power.

Abstract: A thin film transistor array panel includes: a data line which extends in a column direction and transfers a data voltage; a first pixel electrode and a second pixel electrode connected to the data line and adjacent in a row direction; a first thin film transistor connected to the first pixel electrode and the data line, and including a first source electrode and a first drain electrode; and a second thin film transistor connected to the second pixel electrode and the data line, and including a second source electrode and a second drain electrode. The first pixel electrode is at the right of the data line, the second pixel electrode is at the left of the data line, and relative positions of the first source electrode and the first drain electrode are the same as relative positions of the second source electrode and the second drain electrode.