Abstract: Apparatuses, systems, and techniques to perform effective tone management for image data. In an embodiment, a set of contrast gain curves are generated corresponding to a set of tonal ranges of an input image. An output image may then be generated by at least applying corresponding contrast gain curves to tonal ranges of the input image.

Abstract: A memory device includes a first sub-block including word lines, a second sub-block including word lines, and a peripheral circuit configured to apply voltages to the word lines of the first sub-block and the word lines of the second sub-block. The memory device also includes control logic configured to control the peripheral circuit to perform a partial program operation of storing data in the first sub-block, when a plurality of memory cells included in the first sub-block are erased and a plurality of memory cells included in the second sub-block are programmed. The control logic includes a program operation controller for controlling the peripheral circuit to apply a verify operation to a selected word line of the word lines of the first sub-block and then apply a voltage having a constant level to the word lines of the second sub-block in the partial program operation.

Abstract: An upper rail device for a seat of a vehicle includes: a lower plate in which a slot is formed, a drive housing mounted on the lower plate, a drive support that passes through the slot for insertion into a curved movement path of a lower rail, a motor with a reducer mounted on an upper surface of the drive housing, a drive shaft connected to an output portion of the reducer, a drive gear mounted on a lower end portion of the drive shaft and engaged with a driven gear mounted within the curved movement path of the lower rail. The upper rail device may be fastened to enable sliding movement along the curved movement path of the lower rail so that the seat can be moved in a diagonal or oblique direction depending on various purposes, which can improve a seat position movement adjustment.

Abstract: A semiconductor device includes a memory cell array and a peripheral circuit. The memory cell array is coupled to a plurality of word lines and a plurality of bit lines. The peripheral circuit performs a deep-erase verification operation to determine whether a target memory cell has a threshold voltage that is lower than a first negative reference voltage by applying a second negative reference voltage that is lower than the first negative reference voltage to the target memory cell.

Abstract: A method of managing identification information of a drone may include: generating an access message, wherein the access message includes an identifier for the ground identification device, which is a transmitter, an identifier for a receiver, an execution function command for classifying and defining a function to be performed, a serial number for transmitting information sequentially and retransmitting the information when transmission fails, data size information for informing a size of data to be transmitted, and transmission data; and transmitting the access message to an integrated management system corresponding to the identifier for the receiver.

Abstract: A memory device includes a first sub-block including word lines, a second sub-block including word lines, and a peripheral circuit configured to apply voltages to the word lines of the first sub-block and the word lines of the second sub-block. The memory device also includes control logic configured to control the peripheral circuit to perform a partial program operation of storing data in the first sub-block, when a plurality of memory cells included in the first sub-block are erased and a plurality of memory cells included in the second sub-block are programmed. The control logic includes a program operation controller for controlling the peripheral circuit to apply a verify operation to a selected word line of the word lines of the first sub-block and then apply a voltage having a constant level to the word lines of the second sub-block in the partial program operation.

Abstract: A memory device comprising: a memory cell array including memory cells coupled between a word line and a plurality of bit lines, and a control unit suitable for performing a program operation of repeating a program loop including a voltage application operation and a verification operation on the memory cells according to an Incremental Step Pulse Program (ISPP) method until the program operation is performed successfully, wherein the control unit repeatedly performs the program loop by setting a voltage level of an initial program pulse to one of first and second levels according to whether the program operation is an overwrite operation or not, wherein the initial program pulse is to be applied to the word line in the voltage application operation included in an initial program loop of the repeated program loops, and wherein the second level is lower than the first level by a first set level.

Abstract: Disclosed are a method and device for bidirectional communication in a wireless LAN. The method of a first STA comprises the steps of: receiving, from an AP, a first frame including an information element indicating TXOP sharing; confirming a shared TXOP duration on the basis of the first frame; and communicating with a second STA within the shared TXOP duration.

Abstract: A method and apparatus for NSTR communication in a communication system supporting multiple links are disclosed. A method for a first device comprises the steps of: if a first backoff operation has succeeded on a first link belonging to a first pair of NSTR links on which an STR operation of a second device is not supported, transmitting a first data frame to the second device on the first link; performing a second backoff operation for transmission of a second data frame on a second link belonging to the first pair of NSTR links; if the second backoff operation has succeeded on the second link, identifying whether or not a transmission operation of the second device is performed on the first link belonging to the pair of NSTR links; and transmitting the second data frame to the second device on the second link.

Abstract: A method and a device for direct communication in a communication system supporting multiple links are disclosed. A method of an AP MLD comprises the steps of: transmitting a trigger frame in multiple links including a first link and a second link; receiving a response frame for the trigger frame from a first STA associated with an STA MLD in the first link; receiving a first data frame from a third STA in the second link; and when a subject to receive the first data frame is a second STA associated with the STA MLD, transmitting a second data frame generated on the basis of the first data frame, to the first STA in the first link.

Abstract: A memory device applies voltage to drain select lines, which are determined individually. A program operation control unit applies a precharge voltage to a drain select line coupled to a cell string selected from the first cell string and the second cell string before a program voltage is applied to the word line, during a time determined depending on a resistance value of the drain select line coupled to the selected cell string.

Abstract: A semiconductor device may include a plurality of transfer circuits configured to transfer a program pulse to at least one of a plurality of word lines based on a transfer control signal, a decoder configured to provide the program pulse to at least one of the plurality of transfer circuits based on a row address, and a control circuit configured to adjust a voltage level of the transfer control signal based on a program/erase count.

Abstract: A method and a device for shard communication in a wireless LAN are disclosed. A method of a first STA comprises the steps of: receiving a first frame for allocation of a shared communication period from an AP; identifying the shared communication period on the basis of one or more fields included in the first frame; and performing shared communication with a second STA in the shared communication period, wherein the shared communication period is configured within a TXOP configured between the AP and a third STA.

Abstract: A memory device may include: a control circuit suitable for performing a program loop including a program operation including a program voltage application operation on a selected word line and a bit line setup operation on a plurality of bit lines and a verification operation of applying (N?1) first verification voltages to the selected word line according to a predetermined order to check N types of first program states for each of a plurality of memory cells included in the selected word line; and control logic suitable for controlling the control circuit to repeatedly perform the program loop until programming for the selected word line is completed, and controlling the control circuit to apply any one of N types of column voltages to each of the plurality of bit lines in the bit line setup operation included in a second program loop.

Abstract: The present technology relates to an electronic device. A memory device including a plurality of memory cells connected to a plurality of word lines arranged between a plurality of source select lines and a plurality of drain select lines, a peripheral circuit configured to perform a program operation of programming data in selected memory cells among the plurality of memory cells, and a program operation controller configured to control the peripheral circuit to apply a voltage, for turning on or off source select transistors connected to the plurality of source select lines, to the plurality of source select lines, while applying a pass voltage to the plurality of word lines after applying a program voltage to selected word lines connected to the selected memory cells.

Abstract: A memory device may include: a control circuit suitable for performing a program loop including a program operation including a program voltage application operation on a selected word line and a bit line setup operation on a plurality of bit lines and a verification operation of applying (N?1) first verification voltages to the selected word line according to a predetermined order to check N types of first program states for each of a plurality of memory cells included in the selected word line; and control logic suitable for controlling the control circuit to repeatedly perform the program loop until programming for the selected word line is completed, and controlling the control circuit to apply any one of N types of column voltages to each of the plurality of bit lines in the bit line setup operation included in a second program loop.

Abstract: Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on selected memory cells coupled to a selected word line among the plurality of memory cells. The control logic may control the program operation of the peripheral circuit. The program operation may include a plurality of program loops. Each of the program loops may include a program phase and a verify phase. The verify phase may include one or more verify operations. The control logic may be further configured to count a number of the verify operations performed by the peripheral circuit in the verify phase included in one of the plurality of program loops during the program operation.

Abstract: A memory device, and a method of operating the memory device, includes a memory block in which a plurality of cell pages are coupled to each of word lines. The memory device also includes a peripheral circuit configured to adjust a time point at which a verify voltage is applied to a selected word line among the word lines according to an order of performing a program operation during a verify operation of a selected cell page. The memory device further includes a control logic circuit configured to transmit, to the peripheral circuit, an operation code for adjusting a time point at which the verify voltage is output.

Abstract: Apparatuses, systems, and techniques to perform effective tone management for image data. In an embodiment, a set of contrast gain curves are generated corresponding to a set of tonal ranges of an input image. An output image may then be generated by at least applying corresponding contrast gain curves to tonal ranges of the input image.

Abstract: An operating method of a memory device, comprises: a program operation of applying a program voltage to a selected word line to program selected memory cells connected to the selected word line, a first verification operation of applying a first verification voltage to the selected word line and applying a first verification pass voltage to unselected word lines to verify a first program state of the selected memory cells, and a second verification operation of applying a second verification voltage to the selected word line and applying a second verification pass voltage to the unselected word lines to verify a second program state higher than the first program state.