Abstract: Disclosed are a navigation apparatus having lane recognition function and a method for the same. The navigation apparatus may comprise an image acquisition part configured to acquire an image about lanes; and a control part configured to recognize a lane in which a vehicle on driving is located and to provide lane guidance information based on the recognized lane and a configured driving route. Thus, lane change guidance information can be provided in consideration of the number of lanes and distances between intersection points thereby enabling users to drive more stably and efficiently in complex areas.

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract: A plurality of masters arbitrate for access to a shared memory device, such as a SDRAM (synchronous dynamic random access memory), amongst themselves using software and arbitration interfaces. The masters generate additional commands upon arbitration, such as MRS and PALL commands, for prevention of collision of commands, refresh starvation, and/or a missing pre-charge operation in the shared memory device.

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract: An image sensor including a noise removing unit may sense images accurately by measuring the amount of noise generated when the image sensor does not perform a sensing operation, storing information about the measured noise amount in each pixel, and removing photocharge corresponding to the information about the measured noise amount during image sensing.

Abstract: A three-dimensional (3D) image sensor includes a plurality of color pixels, and a plurality of distance measuring pixels. Where the plurality of color pixels and the plurality of distance measuring pixels are arranged in an array, and a group of distance measuring pixels, from among the plurality of distance measuring pixels, are disposed so that a corner of each distance measuring pixel in the group of distance-measuring pixels is adjacent to a corner of an adjacent distance-measuring pixel in the group of distance-measuring pixels. The group of distance measuring pixels is capable of jointly outputting one distance measurement signal.

Abstract: A code encoding apparatus includes a delay circuit and a code generator. The delay circuit generates delayed information based on p-bit input information received in parallel. The delayed information is generated according to a clock. The code generator generates n·p-bit code based on at least one of the input information and the delayed information, where n is a rational number.

Abstract: A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system.

Abstract: A route search method considering the linearity of a route includes: once an arriving is inputted, searching a route to the arriving; when the searched routes are more than two, obtaining linear type information for each of the searched routes; and selecting one of the routes according to the linear type information.

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract: Provided is a vehicle minor apparatus operated in conjunction with left/right mirrors of a vehicle. The vehicle mirror apparatus may include a traveling information collection unit to detect a peripheral vehicle located in lateral and rear sides of the vehicle, and to collect traveling information corresponding to the detected peripheral vehicle, and a first display unit to display the collected traveling information using a plurality of light emitting diodes (LEDs) arranged in a matrix type.

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract: A nonvolatile memory device is provided. In the nonvolatile memory device, a semiconductor substrate of a first conductivity type includes first and second fins. A common bit line electrode connects one end of the first fin to one end of the second fin. Control gate electrodes cover the first and second fins and expand across the top surface of each of the first and second fins. A first string selection gate electrode positioned between the common bit line electrode and the control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins. A second string selection gate electrode positioned between the first string selection gate electrode and the control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins.

Abstract: Provided are a memory cell programming method and a semiconductor device which may be capable of simultaneously writing a bit of data and then another bit of the data to a plurality of memory blocks. The memory programming method, in which M bits of data are written to a plurality of memory blocks, may include a data division operation and a data writing operation where M may be a natural number. In the data division operation, the plurality of memory blocks may be divided into a plurality of memory block groups. In the data writing operation, an ith bit of the data may be simultaneously written to two or more memory block groups from among the plurality memory block groups, and then an i+1th bit of the data may be simultaneously written to the two or more memory block groups from among the plurality memory block groups, where i is a natural number less than M.

Abstract: A method of programming a non-volatile memory cell includes programming a first bit of multi-bit data by setting a threshold voltage of the non-volatile memory cell to a first voltage level within a first of a plurality of threshold voltage distributions. A second bit of the multi-bit data is programmed by setting the threshold voltage to a second voltage level based on a value of the second bit. The second voltage level is the same as the first voltage level if the second bit is a first value and the second voltage level is within a second of the plurality of threshold voltage distributions if the second bit is a second value. A third bit of the multi-bit data is programmed by setting the threshold voltage to a third voltage level based on a value of the third bit.

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract: Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.

Abstract: An image sensor including a noise removing unit may sense images accurately by measuring the amount of noise generated when the image sensor does not perform a sensing operation, storing information about the measured noise amount in each pixel, and removing photocharge corresponding to the information about the measured noise amount during image sensing.

Abstract: Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus includes a page buffer configured to store first data of the page programming operation, an input control unit configured to determine whether to invert the first data based on a number of bits having a first value and a number of bits having a second value. The input control unit is further configured to invert the first data to generate second data if the number of bits having a first value is greater than the number of bits having a second value and store the second data in the page buffer. The multi-bit programming apparatus further includes a page programming unit configured to program the second data stored in the page buffer in at least one multi-bit cell.

Abstract: Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may include: a first control unit that allocates any one of 2N threshold voltage states to the N-bit data; a second control unit that spaces, by any one of a first interval and a second interval, adjacent threshold voltage states of the 2N threshold voltage states; and a programming unit that programs the N-bit data by generating, in each of the at least one multi-bit cell, a distribution state corresponding to the allocated threshold voltage state. The multi-bit programming apparatus can reduce an error rate when reading data.