Patents by Inventor Sungjoon Kim
Sungjoon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8892825Abstract: A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.Type: GrantFiled: March 25, 2013Date of Patent: November 18, 2014Assignee: Silicon Image, Inc.Inventors: Alan Ruberg, Seung-jong Lee, Hyung Rok Lee, Daeyun Shim, Dongyun Lee, Sungjoon Kim, Anu Murthy
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Patent number: 8796185Abstract: A method for fabricating a universal substrate for attaching biomolecules, including sequencing features and the resulting substrate. A method of direct detection of analytes utilizes a Complementary Metal Oxide Semiconductor (CMOS) sensor with the substrate.Type: GrantFiled: March 8, 2012Date of Patent: August 5, 2014Assignee: Lightspeed Genomics, Inc.Inventors: Dae Hyun Kim, Sungjoon Kim
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Publication number: 20140115414Abstract: A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface.Type: ApplicationFiled: December 31, 2013Publication date: April 24, 2014Applicant: Silicon Image, Inc.Inventors: Chinsong Sul, Sungjoon Kim
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Patent number: 8667354Abstract: A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface.Type: GrantFiled: February 25, 2013Date of Patent: March 4, 2014Assignee: Silicon Image, Inc.Inventors: Chinsong Sul, Sungjoon Kim
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Publication number: 20130282991Abstract: A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.Type: ApplicationFiled: March 25, 2013Publication date: October 24, 2013Inventors: Alan Ruberg, Seoung Jeong Lee, Hyung Rok Lee, Daeyun Shim, Dongyun Lee, Sungjoon Kim, Anu Murthy
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Publication number: 20130173974Abstract: A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface.Type: ApplicationFiled: February 25, 2013Publication date: July 4, 2013Applicant: Silicon Image, Inc.Inventors: Chinsong Sul, Sungjoon Kim
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Patent number: 8407427Abstract: A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.Type: GrantFiled: October 23, 2009Date of Patent: March 26, 2013Assignee: Silicon Image, Inc.Inventors: Alan Ruberg, Seoung Jeong Lee, Hyung Rok Lee, Daeyun Shim, Dongyun Lee, Sungjoon Kim, Anu Murthy
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Patent number: 8386867Abstract: A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface.Type: GrantFiled: July 2, 2009Date of Patent: February 26, 2013Assignee: Silicon Image, Inc.Inventors: Chinsong Sul, Sungjoon Kim
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Publication number: 20120231974Abstract: A method for fabricating a universal substrate for attaching biomolecules, including sequencing features and the resulting substrate. A method of direct detection of analytes utilizes a Complementary Metal Oxide Semiconductor (CMOS) sensor with the substrate.Type: ApplicationFiled: March 8, 2012Publication date: September 13, 2012Applicant: LIGHTSPEED GENOMICS, INC.Inventors: Dae Hyun Kim, Sungjoon Kim
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Patent number: 8160192Abstract: A clock and data recovery (CDR) system and method for recovering timing information and data from a serial data stream. The CDR system includes a sampling circuit that produces a recovered clock/data signal and an interleaving feedback network that provides feedback to the sampling circuit. The feedback network includes a logic circuit that produces control signals based on the recovered clock/data signal, a first multiplexer that selects from four phases of a global clock signal based on a control signal, a first delay-locked loop having a first set of delay cells coupled to a second multiplexer that produces a delayed signal based on the selected global clock signal, and a second delay-locked loop having a second set of delay cells that produces a set of phase-shifted feedback signals that are applied to the sampling circuit to phase-align the sampling circuit with the transitions in the received serial data stream.Type: GrantFiled: September 25, 2007Date of Patent: April 17, 2012Assignee: Silicon Image, Inc.Inventors: Dongyun Lee, Sungjoon Kim
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Patent number: 7949863Abstract: A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each port. When a first component coupled to a first port of the memory device wants to communicate with a second component coupled to a second port of the memory device, the first component writes a message to a message buffer associated with the second port. An interrupt in the input register of the second port is set to notify the second component coupled to the second port that a new message is available. Upon receiving the interrupt, the second component reads the interrupt register to determine the nature of the interrupt. The second component then reads the message from the message buffer.Type: GrantFiled: March 30, 2007Date of Patent: May 24, 2011Assignee: Silicon Image, Inc.Inventors: Alan T. Ruberg, Dae Kyeung Kim, Daeyun Shim, Dongyun Lee, Myung Rai Cho, Sungjoon Kim
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Patent number: 7908501Abstract: A method and system for progressively reducing the power consumption of a serial memory device is provided, called the power control system. The power control system monitors the ports of a multi-port serial memory so that they can be enabled or disabled on a per-port basis. When data is not being transmitted or received on a port, a series of steps are taken to progressively de-power portions of the port and cause the port to enter into a low-power state. By disabling certain ports and placing ports in a low-power state, the power consumption of the overall serial port memory is significantly reduced.Type: GrantFiled: March 23, 2007Date of Patent: March 15, 2011Assignee: Silicon Image, Inc.Inventors: Sungjoon Kim, Dongyun Lee, Edward Kim
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Publication number: 20100106917Abstract: A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.Type: ApplicationFiled: October 23, 2009Publication date: April 29, 2010Inventors: Alan Ruberg, Seoung Jeong Lee, Hyung Rok Lee, Daeyun Shim, Dongyun Lee, Sungjoon Kim, Anu Murthy
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Patent number: 7639561Abstract: A multi-port memory device having two or more ports wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock and a port clock. The system clock is applied to port logic that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.Type: GrantFiled: March 30, 2007Date of Patent: December 29, 2009Assignee: Silicon Image, Inc.Inventors: Dongyun Lee, Myung Rai Cho, Sungjoon Kim
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Publication number: 20080235528Abstract: A method and system for progressively reducing the power consumption of a serial memory device is provided, called the power control system. The power control system monitors the ports of a multi-port serial memory so that they can be enabled or disabled on a per-port basis. When data is not being transmitted or received on a port, a series of steps are taken to progressively de-power portions of the port and cause the port to enter into a low-power state. By disabling certain ports and placing ports in a low-power state, the power consumption of the overall serial port memory is significantly reduced.Type: ApplicationFiled: March 23, 2007Publication date: September 25, 2008Inventors: Sungjoon Kim, Dongyun Lee, Edward Kim
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Publication number: 20080075222Abstract: A clock and data recovery (CDR) system and method for recovering timing information and data from a serial data stream. The CDR system includes a sampling circuit that produces a recovered clock/data signal and an interleaving feedback network that provides feedback to the sampling circuit. The feedback network includes a logic circuit that produces control signals based on the recovered clock/data signal, a first multiplexer that selects from four phases of a global clock signal based on a control signal, a first delay-locked loop having a first set of delay cells coupled to a second multiplexer that produces a delayed signal based on the selected global clock signal, and a second delay-locked loop having a second set of delay cells that produces a set of phase-shifted feedback signals that are applied to the sampling circuit to phase-align the sampling circuit with the transitions in the received serial data stream.Type: ApplicationFiled: September 25, 2007Publication date: March 27, 2008Inventors: Dongyun Lee, Sungjoon Kim
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Publication number: 20070245094Abstract: A multi-port memory device having two or more ports wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock and a port clock. The system clock is applied to port logic that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.Type: ApplicationFiled: March 30, 2007Publication date: October 18, 2007Applicant: Silicon Image, Inc.Inventors: Dongyun Lee, Myung Cho, Sungjoon Kim
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Publication number: 20070234021Abstract: A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each port. When a first component coupled to a first port of the memory device wants to communicate with a second component coupled to a second port of the memory device, the first component writes a message to a message buffer associated with the second port. An interrupt in the input register of the second port is set to notify the second component coupled to the second port that a new message is available. Upon receiving the interrupt, the second component reads the interrupt register to determine the nature of the interrupt. The second component then reads the message from the message buffer.Type: ApplicationFiled: March 30, 2007Publication date: October 4, 2007Applicant: Silicon Image, Inc.Inventors: Alan Ruberg, Dae Kim, Daeyun Shim, Dongyun Lee, Myung Cho, Sungjoon Kim
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Publication number: 20070216210Abstract: A motor vehicle seat lift assembly includes a seat pan and a seat frame positioned beneath the seat pan. Each of a pair of first linking members has a first end pivotally secured to the seat pan and a second end pivotally secured to the seat frame. Each of a pair of second linking members has a first end pivotally secured to the seat pan and a second end pivotally secured to the seat frame. A pinion gear is rotatable with respect to the seat pan. An actuator is operably connected to the pinion gear. A rack member has a plurality of teeth, with the pinion gear meshing with the teeth of the rack member. A first end of the rack member is pivotally secured to the first end of one of the first linking members and a second end of the rack member is slidably connected to the seat pan.Type: ApplicationFiled: March 20, 2006Publication date: September 20, 2007Inventors: Hyunkyu Kim, Sungjoon Kim, Sebastien Cabrit
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Patent number: 7252944Abstract: This invention provides methods for identifying novel SHMT modulators. The methods comprise first screening test agents for modulators of p38 activity and then further screening the identified modulating agents for modulators of SHMT enzyme activity. The invention further provides methods and pharmaceutical compositions for modulating cellular proliferation and for treating tumors using the novel SHMT modulators.Type: GrantFiled: July 30, 2004Date of Patent: August 7, 2007Assignee: IRM LLCInventors: Kavita Shah, Sungjoon Kim