Patents by Inventor Sung-We Cho
Sung-We Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11287474Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.Type: GrantFiled: August 27, 2019Date of Patent: March 29, 2022Assignee: Samsung Electronics Co., LtdInventors: Ha-Young Kim, Sung-We Cho, Dal-Hee Lee, Jae-Ha Lee
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Patent number: 11189639Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.Type: GrantFiled: April 8, 2020Date of Patent: November 30, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ha-young Kim, Chang-beom Kim, Hyun-jeong Roh, Tae-joong Song, Dal-hee Lee, Sung-we Cho
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Patent number: 11031385Abstract: An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.Type: GrantFiled: December 23, 2019Date of Patent: June 8, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Woo Seo, Jin Tae Kim, Tae Joong Song, Hyoung-Suk Oh, Keun Ho Lee, Dal Hee Lee, Sung We Cho
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Patent number: 10990740Abstract: An integrated circuit may include a first standard cell including first and second active regions extending in a first horizontal direction and a first gate line extending in a second horizontal direction orthogonal to the first horizontal direction; and a second standard cell including third and fourth active regions extending in the first horizontal direction and a second gate line aligned in parallel to the first gate in the second horizontal direction and being adjacent to the first standard cell. A distance between the second active region of the first standard cell and the third active region of the second standard cell may be greater than a distance between the first and second active regions of the first standard cell, and may be greater than a distance between the third and fourth active regions of the second standard cell.Type: GrantFiled: April 9, 2019Date of Patent: April 27, 2021Inventors: Jin-Tae Kim, Sung-We Cho, Tae-Joong Song, Seung-Young Lee, Jin-Young Lim
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Publication number: 20200235126Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.Type: ApplicationFiled: April 8, 2020Publication date: July 23, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ha-young KIM, Chang-beom Kim, Hyun-jeong Roh, Tae-joong Song, Dal-hee Lee, Sung-we Cho
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Patent number: 10651201Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.Type: GrantFiled: March 6, 2018Date of Patent: May 12, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ha-young Kim, Chang-beom Kim, Hyun-jeong Roh, Tae-joong Song, Dal-hee Lee, Sung-we Cho
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Publication number: 20200126968Abstract: An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.Type: ApplicationFiled: December 23, 2019Publication date: April 23, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jae-Woo SEO, Jin Tae KIM, Tae Joong SONG, Hyoung-Suk OH, Keun Ho LEE, Dal Hee LEE, Sung We CHO
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Publication number: 20200050728Abstract: An integrated circuit may include a first standard cell including first and second active regions extending in a first horizontal direction and a first gate line extending in a second horizontal direction orthogonal to the first horizontal direction; and a second standard cell including third and fourth active regions extending in the first horizontal direction and a second gate line aligned in parallel to the first gate in the second horizontal direction and being adjacent to the first standard cell. A distance between the second active region of the first standard cell and the third active region of the second standard cell may be greater than a distance between the first and second active regions of the first standard cell, and may be greater than a distance between the third and fourth active regions of the second standard cell.Type: ApplicationFiled: April 9, 2019Publication date: February 13, 2020Inventors: JIN-TAE KIM, Sung-We Cho, Tae-Joong Song, Seung-Young Lee, Jin-Young Lim
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Patent number: 10553574Abstract: An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.Type: GrantFiled: October 20, 2016Date of Patent: February 4, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Woo Seo, Jin Tae Kim, Tae Joong Song, Hyoung-Suk Oh, Keun Ho Lee, Dal Hee Lee, Sung We Cho
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Patent number: 10216883Abstract: A computer-implemented method of designing an integrated circuit (IC) includes allocating a plurality of colors to a plurality of patterns corresponding to one layer of a first cell so that a multi-patterning technology is designated for use in forming the plurality of patterns, the first cell being a multi-height cell corresponding to a plurality of rows, generating a plurality of shift cells, in which a color remapping operation associated with the plurality of patterns is performed for each row, with respect to the first cell, and storing a cell set including the first cell and the plurality of shift cells in a standard cell library.Type: GrantFiled: November 15, 2016Date of Patent: February 26, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Ha-Young Kim, Sung-We Cho, Tae-Joong Song
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Publication number: 20180294280Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.Type: ApplicationFiled: March 6, 2018Publication date: October 11, 2018Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ha-young KIM, Chang-beom KIM, Hyun-jeong ROH, Tae-joong SONG, Dal-hee LEE, Sung-we CHO
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Patent number: 9905561Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically cType: GrantFiled: January 18, 2017Date of Patent: February 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ha-young Kim, Sung-we Cho, Tae-joong Song, Sang-hoon Baek
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Publication number: 20170294430Abstract: An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.Type: ApplicationFiled: October 20, 2016Publication date: October 12, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Jae-Woo SEO, Jin Tae KIM, Tae Joong SONG, Hyoung-Suk OH, Keun Ho LEE, Dal Hee LEE, Sung We CHO
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Publication number: 20170277819Abstract: A computer-implemented method of designing an integrated circuit (IC) includes allocating a plurality of colors to a plurality of patterns corresponding to one layer of a first cell so that a multi-patterning technology is designated for use in forming the plurality of patterns, the first cell being a multi-height cell corresponding to a plurality of rows, generating a plurality of shift cells, in which a color remapping operation associated with the plurality of patterns is performed for each row, with respect to the first cell, and storing a cell set including the first cell and the plurality of shift cells in a standard cell library.Type: ApplicationFiled: November 15, 2016Publication date: September 28, 2017Inventors: HA-YOUNG KIM, SUNG-WE CHO, TAE-JOONG SONG
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Patent number: 9665678Abstract: A method of designing an integrated circuit includes a processor receiving input data initially-defining the integrated circuit using a plurality of first standard cells designed to optimize a performance or yield characteristic. The processor substitutes at least one second standard cell designed to optimize a different performance or yield characteristic from that for which the first standard cells were optimized for a corresponding one of the first standard cells. The processor generates output data defining the integrated circuit including the second standard cell. The substituted second standard cell has the same function as the corresponding first standard cell for which it was substituted.Type: GrantFiled: June 19, 2015Date of Patent: May 30, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-we Cho, Dal-hee Lee, Ha-young Kim, Jae-woo Seo, Jin-tae Kim
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Publication number: 20170133380Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically cType: ApplicationFiled: January 18, 2017Publication date: May 11, 2017Inventors: Ha-young KIM, Sung-we CHO, Tae-joong SONG, Sang-hoon BAEK
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Patent number: 9583493Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically cType: GrantFiled: April 7, 2016Date of Patent: February 28, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ha-young Kim, Sung-we Cho, Tae-joong Song, Sang-hoon Baek
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Publication number: 20160300839Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically cType: ApplicationFiled: April 7, 2016Publication date: October 13, 2016Inventors: Ha-young Kim, Sung-we Cho, Tae-joong Song, Sang-hoon Baek
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Publication number: 20160034627Abstract: A method of designing an integrated circuit includes a processor receiving input data initially-defining the integrated circuit using a plurality of first standard cells designed to optimize a performance or yield characteristic. The processor substitutes at least one second standard cell designed to optimize a different performance or yield characteristic from that for which the first standard cells were optimized for a corresponding one of the first standard cells. The processor generates output data defining the integrated circuit including the second standard cell. The substituted second standard cell has the same function as the corresponding first standard cell for which it was substituted.Type: ApplicationFiled: June 19, 2015Publication date: February 4, 2016Inventors: Sung-we Cho, Dal-hee Lee, Ha-young Kim, Jae-woo Seo, Jin-tae Kim
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Patent number: 7301381Abstract: A clocked state circuit can include a transmission gate configured to clock an output of a master terminal to an input of a slave terminal responsive to a clock signal or a delayed clock signal coupled to the transmission gate.Type: GrantFiled: August 1, 2005Date of Patent: November 27, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Young-chul Rhee, Sung-we Cho