Abstract: A three-port receptacle connects both single-prong and three-prong electrical connectors of electrosurgical accessories to an electrosurgical generator. The receptacle includes two control ports for accepting the two control prongs of the three-prong connector and an energy-delivery port for accepting the energy-conducting prong of the three-prong connector. The energy-delivery port also receives an energy-conducting prong of a single-prong connector. A single contact assembly is located behind the energy-delivery port and delivers electrosurgical power to the energy-conducting prongs of both types of accessory connectors.

Abstract: Apparatus and method for emulating a virtual machine within the physical memory space of a programmable processor using virtual functions having a format independent of the hardware architecture of the processor. The virtual functions are executed using an execution engine emulated in the processor. A symbol table maps the virtual functions to native functions in the memory space, and a gate call interface block accesses the symbol table and initiates execution of the corresponding native function in response to each executed virtual function. Execution of the corresponding native function operates to evaluate the concurrent execution of at least one other native function. In this way for example, standardized platform virtual code can be generated for a number of different types of processors and used to evaluate the native operational routines of each processor.

Abstract: A network device to maintain resource management within a network may comprise an emulator or watchdog that may send an emulation request to a resource manager for emulating a request of a client. Operability of the resource manager may be identified based on a reply of the resource manager to the emulation request. If the resource manager does not provide a response within a given time frame, then the watchdog may identify a failure condition for the resource manager. The watchdog may then initiate corrective actions for replacing the resource manager with a backup server responsive to identifying the fail condition.

Abstract: One embodiment of the invention is an integrated circuit having: (i) an array of flash transistors formed on a substrate and arranged in one or more rows, each flash transistor having a control gate, wherein, in each row, the control gates are connected to a word line; and (ii) for each word line, at least one diode structure formed on the substrate and having first and second diodes, each diode having a cathode and an anode, wherein the word line is connected to the cathode of the first diode and to the anode of the second diode.

Abstract: A process of fabricating a semiconductor device includes forming a device region including a non-volatile memory element and forming a utility layer overlying the device region, where the utility layer is a dielectric material formed by RTCVD. The utility layer preferably has a hydrogen content below that necessary to reduce the data retention of the non-volatile memory element in the device region. The utility layer can function as one or more of an etch-stop layer, a diffusion barrier layer, or an insulating layer.

Abstract: Hybrid antigens comprising at least one antigenic domain, at least one heat shock protein binding domain, and at least one improved peptide linker there between are described which are useful for the induction of an immune response to the antigenic domain when administered alone or in a complex with at least one heat shock protein. The hybrid antigens and complexes can be used to treat infectious diseases and cancers that express an antigen of the antigenic domain.

Abstract: Hybrid antigens comprising an antigenic domain and improved heat shock protein binding domains are described which are useful for the induction of an immune response to the antigenic domain and thus can be used to treat infectious diseases and cancers that express an antigen of the antigenic domain.

Abstract: Apparatus and method for emulating a virtual machine within the physical memory space of a programmable processor using virtual functions having a format independent of the hardware architecture of the processor. The virtual functions are executed using an execution engine emulated in the processor. A symbol table maps the virtual functions to native functions in the memory space, and a gate call interface block accesses the symbol table and initiates execution of the corresponding native function in response to each executed virtual function. Execution of the corresponding native function operates to evaluate the concurrent execution of at least one other native function. In this way for example, standardized platform virtual code can be generated for a number of different types of processors and used to evaluate the native operational routines of each processor.

Abstract: A zero power memory cell includes first and second NMOS transistors and a PMOS transistor, wherein the first NMOS transistor and first PMOS transistor each include a three-implant channel region, and wherein the second NMOS transistor further includes a two-implant channel region.

Abstract: A method for forming a three transistor zero power memory cell including a p-channel sense transistor, an n-channel write transistor, and an n-channel sense transistor including: implanting a p-type impurity into a p-type substrate in which a n-channel high voltage transistor will be formed; implanting an n-type impurity into an n-type well in a p-type substrate in which a p-channel high voltage transistor will be formed; forming a mask to allow implants to occur to p-channel devices; performing a series of n-type dopant implants into the substrate where the p-channel transistors will be formed; growing a high voltage gate oxide; forming a mask to allow implants to occur to n-channel devices, said mask blocking implants to said n-channel sense transistor; and performing a series of p-type implants into the substrate where the n-channel devices will be formed. In addition, a memory cell which may include a first NMOS transistor having a source, drain and gate, and a first PMOS transistor is disclosed.

Abstract: A zero-power electrically erasable and programmable memory cell is implemented in CMOS (complementary metal oxide semiconductor) technology. A P-channel sense transistor has a source coupled to a first voltage generator, and an N-channel sense transistor has a source coupled to a second voltage generator. The drains of the P-channel and N-channel sense transistors are coupled together to form an output of the memory cell, and the gates of the P-channel and N-channel sense transistor are coupled together to form a floating gate of the memory cell. In an example embodiment of the present invention, each of the first and second voltage generators are variable voltage generators that apply a positive voltage at the respective source of each of the P-channel and N-channel sense transistors during the erase operation and/or that apply a ground or negative voltage at the respective source of each of the P-channel and N-channel sense transistors during the program operation.

Abstract: An improved manufacturing process and an improved device made by the process are described for forming via interconnects between metal layers in a multilevel metallization structure. This process essentially eliminates exploding vias due to vias extending beyond the edge of metal lines. The strong reaction is caused by the chemical interaction of metal lines beneath vias with reactants and/or reaction products associated with via fill. An insulating cap layer is deposited on the patterned and etched metal layer before depositing the interlevel dielectric layer above it. A two-step via etch process selectively removes portions of the cap layer within vias prior to via fill. The remaining cap layer within the vias covers, and thereby protects, otherwise vulnerable underlying metal from the damaging chemical interaction during via fill. Using this process, metal borders around vias can be reduced or eliminated, thereby increasing circuit packing density.

Abstract: A non-volatile memory cell is disclosed with increased drive current. A low voltage read transistor is used to increase the drive current. However, with a low voltage read transistor, extra protection is needed to ensure the read transistor is not damaged by high voltage. In one aspect, an isolation transistor is inserted between the read transistor and a sense transistor. The isolation transistor, read transistor and sense transistor are connected in series. When a high voltage is used during an erase operation of the memory cell, the isolation transistor absorbs some of the voltage to protect the read transistor from an excessive voltage level.

Abstract: Zero-power logic cells are implemented in CMOS technology for forming part of programmable logic devices with minimized static power dissipation. The zero-power logic cells are implemented with stacked P-channel and N-channel field effect transistors. The respective gate of each of such P-channel and N-channel transistors are coupled to one of a first input signal, a second input signal, an output of a first memory cell, or an output of a second memory cell. The output node of the logic cell is one of a logic cell input signal, a complement of the logic cell input signal, the logical high state, or the logical low state depending on the outputs of the memory cells in a functional mode. In addition, such zero-power logic cells may be used to verify the respective output of each of the first and second memory cells in a verify mode.

Abstract: The invention relates to a method of potentiating cell damage in a target cell population by administering a “restraining agent” and concomitantly or subsequently applying a “targeted cytotoxic insult.” The restraining agent is administered at a concentration and under conditions sufficient to retard, but not to arrest, the progress of the target cell population through the cell cycle, a concept termed “dynamic retardation.” With such a mechanism, all the cells intended for damage by the targeted cytotoxic insult are likely to cycle into the relevant interval of vulnerability (target interval) within the cell cycle, resulting in a larger number of susceptible cells, and the time period during which those cells are vulnerable to the action of a given targeted cytotoxic insult is increased, resulting in a higher probability and percentage of cell killing.

Abstract: A nitride layer is deposited over a field oxide layer used to separate transistors formed in a substrate, the nitride layer serving to decrease transistor current leakage. The nitride layer has a dense lattice, effectively blocking H+ and Na+ penetration from overlying layers into the field oxide. Positive ions such as H+ and Na+ penetrating into the field oxide layer cause a p-substrate under the field oxide layer to become inverted or act like an n-type substrate, creating leakage current between source and drain regions of transistors which the field oxide layer separates. When high transistor threshold voltages such as 12 volts or more are desired, the nitride layer provides a significant reduction in current leakage.

Abstract: The present invention provides a method and system for providing electrical insulation for local interconnect in a logic circuit. A system and method according to the present invention for providing electrical installation for local interconnects during manufacturing of a logic circuit comprising the steps of providing a first layer of material over a semiconductor wafer and providing a second layer of material over the first layer. Additionally, a photoresist material is provided over a portion of the logic circuit to be electrically insulated. Portions of the first and second layers which are unprotected by the photoresist material are then etched. At least a third layer is then provided over the first and second layers, and the third layer is etched such that the first layer as an electrical insulation over the portion of the logic circuit.

Abstract: The present invention provides a method and system for providing electrical insulation for local interconnect in a logic circuit. A system and method according to the present invention for providing electrical installation for local interconnects during manufacturing of a logic circuit comprising the steps of providing a first layer of material over a semiconductor wafer and providing a second layer of material over the first layer. Additionally, a photoresist material is provided over a portion of the logic circuit to be electrically insulated. Portions of the first and second layers which are unprotected by the photoresist material are then etched. At least a third layer is then provided over the first and second layers, and the third layer is etched such that the first layer as an electrical insulation over the portion of the logic circuit.

Abstract: The invention relates to a method of potentiating cell damage in a target cell population by administering a “restraining agent” and concomitantly or subsequently applying a “targeted cytotoxic insult.” The restraining agent is administered at a concentration and under conditions sufficient to retard, but not to arrest, the progress of the target cell population through the cell cycle, a concept termed “dynamic retardation.” With such a mechanism, all the cells intended for damage by the targeted cytotoxic insult are likely to cycle into the relevant interval of vulnerability (target interval) within the cell cycle, resulting in a larger number of susceptible cells, and the time period during which those cells are vulnerable to the action of a given targeted cytotoxic insult is increased, resulting in a higher probability and percentage of cell killing.

Abstract: Borderless vias are formed by depositing a hard dielectric mask layer on the upper surface of a lower metal feature and forming sidewall spacers on the side surfaces of the metal feature and mask layer. A dielectric interlayer is deposited and a misaligned through-hole formed therein by etching. The dielectric material of the sidewall spacer and dielectric material of the dielectric interlayer are different. The etchant employed to form the through-hole exhibits a high selectivity with respect to the sidewall spacer material. The dielectric mask layer enables the formation of a sidewall spacer extending above the metal feature such that, after etching to form the misaligned through-hole, the sidewall spacer covers the side surface of the metal feature.