Abstract: A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes a floating gate with high data retention. A tungsten damascene local interconnect structure includes a silicon nitride etch stop layer which is formed using Plasma Enhanced Chemical Vapor Deposition (PECVD) at a temperature of at least 480° C. such that the etch stop layer has a very low concentration of hydrogen ions. The minimization of hydrogen ions, which constitute mobile positive charge carriers, in the etch stop layer, minimizes recombination of the hydrogen ions with electrons on the floating gate, and thereby maximizes data retention of the device.

Abstract: A nitride layer is deposited over a field oxide layer used to separate transistors formed in a substrate, the nitride layer serving to decrease transistor current leakage. The nitride layer has a dense lattice, effectively blocking H+ and Na+ penetration from overlying layers into the field oxide. Positive ions such as H+ and Na+ penetrating into the field oxide layer cause a p-substrate under the field oxide layer to become inverted or act like an n-type substrate, creating leakage current between source and drain regions of transistors which the field oxide layer separates. When high transistor threshold voltages such as 12 volts or more are desired, the nitride layer provides a significant reduction in current leakage.

Abstract: A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes a floating gate with high data retention. A tungsten damascene local interconnect structure includes a silicon nitride etch stop layer which is formed using Plasma Enhanced Chemical Vapor Deposition (PECVD) at a temperature of at least 480° C. such that the etch stop layer has a very low concentration of hydrogen ions. The minimization of hydrogen ions, which constitute mobile positive charge carriers, in the etch stop layer, minimizes recombination of the hydrogen ions with electrons on the floating gate, and thereby maximizes data retention of the device.

Abstract: A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes a floating gate with high data retention. A tungsten damascene local interconnect structure includes a silicon oxynitride etch stop layer which is formed using Plasma Enhanced Chemical Vapor Deposition (PECVD) at a temperature of at least 480.degree. C. such that the etch stop layer has a very low concentration of hydrogen ions. The minimization of hydrogen ions, which constitute mobile positive charge carriers, in the etch stop layer, minimizes recombination of the hydrogen ions with electrons on the floating gate, and thereby maximizes data retention of the device.

Abstract: The present invention provides a method and system for providing electrical insulation for local interconnect in a logic circuit. A system and method according to the present invention for providing electrical installation for local interconnects during manufacturing of a logic circuit comprising the steps of providing a first layer of material over a semiconductor wafer and providing a second layer of material over the first layer. Additionally, a photoresist material is provided over a portion of the logic circuit to be electrically insulated. Portions of the first and second layers which are unprotected by the photoresist material are then etched. At least a third layer is then provided over the first and second layers, and the third layer is etched such that the first layer as an electrical insulation over the portion of the logic circuit.

Abstract: An integrated circuit ("IC") having three different oxide layer thicknesses and a process for manufacturing the IC using a single oxide growth step is provided. A first region is formed on a substrate surface with oxidation enhancing properties. A second region is formed on the substrate surface with a dose of nitrogen that retards oxidation. An oxide layer is grown from the first and the second regions and a third region of the substrate such that the first, second, and third regions yield a first oxide layer for the capacitor, a second oxide layer for the read transistor and a third oxide layer for the write transistor.

Abstract: Borderless vias are formed by depositing a hard dielectric mask layer on the upper surface of a lower metal feature and forming sidewall spacers on the side surfaces of the metal feature and mask layer. A dielectric interlayer is deposited and a misaligned through-hole formed therein by etching. The dielectric material of the sidewall spacer and dielectric material of the dielectric interlayer are different. The etchant employed to form the through-hole exhibits a high selectivity with respect to the sidewall spacer material. The dielectric mask layer enables the formation of a sidewall spacer extending above the metal feature such that, after etching to form the misaligned through-hole, the sidewall spacer covers the side surface of the metal feature.

Abstract: Controlling the thickness of borophosphorous tetraethyl orthosilicate (BPTEOS) used as all or part of the first inter-layer dielectric (ILD0) in manufacturing a semiconductor device containing an array of transistors to control the field leakage between transistors. Reducing field leakage enables the thickness of field oxide, typically used to reduce field leakage, to be reduced to increase device density in the transistor array.

Abstract: A method for forming a uniform and reliable oxide layer on the surface of a semiconductor substrate using projection gas immersion laser doping (P-GILD) is provided. A semiconductor substrate is immersed in an oxide enhancing compound containing atmosphere. The oxide enhancing compound containing atmosphere may include phosphorus, arsenic, boron or an equivalent. A 308 nm excimer laser is then applied to a portion of the substrate to induce incorporation of the oxide enhancing compound into a portion of the substrate. The deposition depth is dependent upon the strength of the laser energy directed at the surface of the substrate. A uniform and reliable oxide layer is then formed on the surface of the substrate by heating the substrate. The laser may be applied with a reflective reticle or mask formed on the substrate. An E.sup.2 PROM memory cell having a program junction region in a silicon substrate is also provided. An oxide layer is positioned between a program junction and a floating gate.

Abstract: A method for improving the endurance and reliability of a floating gate transistor often used in memory applications by controlling the electric field induced across the tunnel oxide region of the floating gate when discharging electrons from the floating gate. The method comprises the steps of: allowing the active region to ground; and applying a program voltage to the floating gate over a period of time and at a magnitude, by increasing the voltage from zero volts to the magnitude over a first period of at least 1 millisecond (ms.), maintaining the voltage at the magnitude for a second period of around 10 ms.-100 ms. sufficient to place charge on the floating gate, and decreasing the voltage from the magnitude during a third period to zero volts in not greater than 50 microseconds.

Abstract: A method of forming an oxide enhancing region, such as phosphorus, in a semiconductor substrate with minimal damage is provided. The method includes the steps of forming an oxide enhancing region in the semiconductor substrate to a depth below the semiconductor substrate. A 308 nm excimer laser is then applied to the oxide enhancing region in order to reduce the damage caused by forming the oxide enhancing region. A uniform and reliable oxide layer is then formed on the surface of the substrate over the damage reduced oxide enhancing region.

Abstract: The concentration of impurities at the surface of the semiconductor device adjacent and under the bird's beak of a field oxide region is reduced by employing sidewall spacers prior to field implantation. The resulting semiconductor device exhibits reduced sidewall junction capacitance and leakage, an increased junction breakdown voltage and a reduced narrow channel effect.

Abstract: A method for isolating regions of a circuit device in a semiconductor substrate. The method generally comprises the steps of: forming a first insulation region and a second insulation region; etching a trench in the first insulation region, the trench extending into the semiconductor substrate to a depth below the surface of the semiconductor substrate; filling the first isolation region with an isolation material and removing a portion of the isolation material such that the trench isolation material fills the trench and has a surface level with the surface of the substrate; and thermally growing a field oxide in the first and second isolation regions. In a further aspect, a semiconductor device is provided. The device is formed on a semiconductor substrate, the substrate having a surface and includes at least a first, second, and third active regions separated by first and second insulating regions.

Abstract: An integrated circuit device and manufacturing process wherein a first region is formed in a substrate with a dopant that enhances oxide formation and a second region is formed in the substrate with a dose of nitrogen that retards oxide formation. An oxide layer is grown over the first and the second regions and over a third region of the substrate such that the first, second, and third regions yield differing thicknesses of the oxide layer.

Abstract: A semiconductor structure includes isolation regions fabricated by a hybrid local oxidation of silicon (LOCOS) technique and a trench isolation technique. Wide and narrow gaps or spacings are etched in a multilayer silicon structure. The wide gaps are covered by a photoresist, and the narrow gaps are further etched to form deep trenches. The wide spacing and deep trenches are filled with an insulative material such as TEOS. The TEOS is etched and the structure is heated to cause local oxidation of silicon in the deep trench and wide spacing. The hybrid fabrication technique is particularly useful in complementary metal oxide semiconductor (CMOS) technology where wide isolation units are utilized to separate transistors sharing the same gate and trenches are utilized to isolate transistors sharing the same well.

Abstract: Increased densification in a semiconductor chip is provided by a negative enclosure of a conductive via utilizing an etch stop insulating material.

Abstract: The concentration of impurities at the surface of the semiconductor device adjacent and under the bird's beak of a field oxide region is reduced by employing sidewall spacers prior to field implantation. The resulting semiconductor device exhibits reduced sidewall junction capacitance and leakage, an increased junction breakdown voltage and a reduced narrow channel effect.

Abstract: A CMOS memory cell including PMOS and NMOS transistors with a common floating gate. The CMOS memory cell includes a first capacitor connecting a first control voltage to the common floating gate and a second tunneling capacitor connected from the common floating gate to the source of the NMOS transistor. The tunneling capacitor includes a tunneling oxide region utilized to charge or discharge the floating gate during program or erase. The CMOS cell further includes a pass transistor with a source to drain path connecting the source of the NMOS transistor to a second control voltage.