Patents by Inventor Sunil K. Singh

Sunil K. Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210175323
    Abstract: A capacitor structure for an integrated circuit (IC) is provided. The capacitor structure includes a plurality of spaced metal pillars with each metal pillar positioned on a corresponding underlying metal wire of an underlying metal layer. A metal-insulator-metal layer is positioned over and between the metal pillars. At least one contact is operatively coupled to a first metal pillar of the plurality of metal pillars. The metal-insulator-metal layer creates a MIM capacitor that undulates over the metal pillars, creating a higher density capacitance compared to conventional planar MIM capacitors. The metal pillars extend into the metal-insulator-metal layer, which reduces contact resistance. The capacitor structure can be integrated into an IC with no major integration issues. A related method is also provided.
    Type: Application
    Filed: December 5, 2019
    Publication date: June 10, 2021
    Inventors: Sunil K. Singh, Eswar Ramanathan
  • Publication number: 20200357880
    Abstract: Embodiments of the disclosure provide a capacitor structure for an integrated circuit (IC), and methods to form the capacitor structure. The capacitor structure may include: a first ring electrode in an inter-level dielectric (ILD) layer on a substrate; an inner electrode positioned within the first ring electrode; and a capacitor dielectric separating the first ring electrode and the inner electrode, and separating a bottom surface of the inner electrode from the ILD layer.
    Type: Application
    Filed: May 10, 2019
    Publication date: November 12, 2020
    Inventors: Dewei Xu, Sunil K. Singh, Siva R. Dangeti, Seung-Yeop Kook
  • Patent number: 10832842
    Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Jagar Singh
  • Patent number: 10818557
    Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Akshey Sehgal, Xinyuan Dou, Sunil K. Singh, Ravi P. Srivastava, Haiting Wang, Scott H. Beasor
  • Patent number: 10777413
    Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over a dielectric layer, and a block mask is formed that is arranged over an area on the hardmask. After forming the block mask, a first mandrel and a second mandrel are formed on the hardmask. The first mandrel is laterally spaced from the second mandrel, and the area on the hardmask is arranged between the first mandrel and the second mandrel. The block mask may be used to provide a non-mandrel cut separating the tips of interconnects subsequently formed in the dielectric layer.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yuping Ren, Guoxiang Ning, Haigou Huang, Sunil K. Singh
  • Patent number: 10741495
    Abstract: In an exemplary method, a first dielectric layer is formed on a substrate. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer is a carbon rich film and different from the first dielectric layer. A trench is formed through the first and second dielectric layers. A conductive line is formed in the trench. A third dielectric layer is formed on the second dielectric layer and conductive line. The material of the third dielectric layer is different from the second dielectric layer. A via opening is formed through the third dielectric layer and stops at the second dielectric layer with a portion of the conductive line exposed to the via opening. At the bottom of the via opening, a recess is formed in the second dielectric layer adjacent to the conductive line. The via opening and recess are filled with a conductive material contacting the conductive line.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: August 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Vinit O. Todi, Shao Beng Law
  • Patent number: 10714380
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ravi P. Srivastava, Sipeng Gu, Sunil K. Singh, Xinyuan Dou, Akshey Sehgal, Zhiguo Sun
  • Patent number: 10643891
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to via structures and via patterning using oblique angle deposition processes. The method includes: depositing a material on a lower wiring layer; forming one or more openings in the material; filling the one or more openings with a conductive material; growing via structures on the conductive material; forming interlevel dielectric material on the via structures; and forming an upper wiring layer on the interlevel dielectric material and in contact with the via structures.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Qanit Takmeel, Somnath Ghosh, Anbu Selvam K M Mahalingam, Craig M. Child, Sunil K. Singh
  • Publication number: 20200135545
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.
    Type: Application
    Filed: October 26, 2018
    Publication date: April 30, 2020
    Inventors: Ravi P. SRIVASTAVA, Sipeng GU, Sunil K. SINGH, Xinyuan DOU, Akshey SEHGAL, Zhiguo SUN
  • Publication number: 20200083099
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to via structures and via patterning using oblique angle deposition processes. The method includes: depositing a material on a lower wiring layer; forming one or more openings in the material; filling the one or more openings with a conductive material; growing via structures on the conductive material; forming interlevel dielectric material on the via structures; and forming an upper wiring layer on the interlevel dielectric material and in contact with the via structures.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 12, 2020
    Inventors: Qanit TAKMEEL, Somnath GHOSH, Anbu Selvam K M MAHALINGAM, Craig M. CHILD, Sunil K. SINGH
  • Publication number: 20200020531
    Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over a dielectric layer, and a block mask is formed that is arranged over an area on the hardmask. After forming the block mask, a first mandrel and a second mandrel are formed on the hardmask. The first mandrel is laterally spaced from the second mandrel, and the area on the hardmask is arranged between the first mandrel and the second mandrel. The block mask may be used to provide a non-mandrel cut separating the tips of interconnects subsequently formed in the dielectric layer.
    Type: Application
    Filed: July 12, 2018
    Publication date: January 16, 2020
    Inventors: Yuping Ren, Guoxiang Ning, Haigou Huang, Sunil K. Singh
  • Publication number: 20200013551
    Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.
    Type: Application
    Filed: August 26, 2019
    Publication date: January 9, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Jagar Singh
  • Publication number: 20200013678
    Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 9, 2020
    Inventors: Sipeng Gu, Akshey Sehgal, Xinyuan Dou, Sunil K. Singh, Ravi P. Srivastava, Haiting Wang, Scott H. Beasor
  • Patent number: 10504774
    Abstract: Methods of lithographic patterning to form interconnect structures for a chip. A hardmask layer is formed on a dielectric layer. A sacrificial layer is formed on the hardmask layer. First opening and second openings are formed in the sacrificial layer that extend through the sacrificial layer to the hardmask layer. A resist layer is formed on the sacrificial layer. An opening is formed in the resist layer that is laterally located between the first opening in the first sacrificial layer and the second opening in the first sacrificial layer. The resist layer is comprised of a metal oxide resist material that is removable selective to the hardmask layer.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: December 10, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Sohan S. Mehta, Sherjang Singh, Ravi P. Srivastava
  • Patent number: 10497610
    Abstract: Methods of lithographic patterning a dielectric layer. A first resist layer is formed on a hardmask layer, and a second resist layer is formed on the first resist layer. The second resist layer is patterned to form a first opening, which is transferred from the second resist layer to the first resist layer. The second resist layer is removed from the first resist layer after the first opening is transferred from the second resist layer to the first resist layer. The first resist layer is patterned to form a second opening laterally displaced in the first resist layer from the first opening. The first resist layer is comprised of a metal oxide photoresist that is removable selective to the hardmask layer. The hardmask layer and the dielectric layer may be subsequently patterned using first resist layer.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: December 3, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ravi Srivastava, Sunil K. Singh
  • Patent number: 10453605
    Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: October 22, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Jagar Singh
  • Publication number: 20190237356
    Abstract: Interconnect structures and methods for forming an interconnect structure. A dielectric layer of a metallization level is deposited and a trench is patterned in the dielectric layer. A sacrificial layer is formed in the trench in the dielectric layer. The sacrificial layer is patterned to form a first trench and a second trench separated from the first trench by a section of the sacrificial layer. A first metal interconnect is formed in the first trench, a second metal interconnect is formed in the second trench, and a porous cap layer is formed over the first metal interconnect, the second metal interconnect, and the section of the sacrificial layer. After forming the porous cap layer, the section of the sacrificial layer is removed.
    Type: Application
    Filed: January 29, 2018
    Publication date: August 1, 2019
    Inventors: Ravi Prakash Srivastava, Sunil K. Singh
  • Publication number: 20190221523
    Abstract: In an exemplary method, a first dielectric layer is formed on a substrate. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer is a carbon rich film and different from the first dielectric layer. A trench is formed through the first and second dielectric layers. A conductive line is formed in the trench. A third dielectric layer is formed on the second dielectric layer and conductive line. The material of the third dielectric layer is different from the second dielectric layer. A via opening is formed through the third dielectric layer and stops at the second dielectric layer with a portion of the conductive line exposed to the via opening. At the bottom of the via opening, a recess is formed in the second dielectric layer adjacent to the conductive line. The via opening and recess are filled with a conductive material contacting the conductive line.
    Type: Application
    Filed: January 18, 2018
    Publication date: July 18, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Vinit O. Todi, Shao Beng Law
  • Patent number: 10353288
    Abstract: A litho-litho-etch double patterning method including forming a resist layer by coating a substrate with a resist composition; exposing the resist layer to a first radiant energy density of UV rays; forming a first pattern in the resist layer by developing the resist layer with a positive developer; exposing the resist layer to a second radiant energy density of UV rays; and forming a second pattern in the resist layer by developing the resist layer with a negative developer, the second pattern including one or more features of the first pattern.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: July 16, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vineet Sharma, Sohan S. Mehta, Craig D. Higgins, Sunil K. Singh, Feng Wang
  • Patent number: 10347528
    Abstract: Methods of forming an interconnect of an IC are disclosed. The methods etch a wire trench opening partially into an ILD layer using a hard mask, and form a metal liner sidewall spacer on sidewalls of the wire trench opening, prior to etching via openings that create a via-wire opening with the wire trench opening. The metal liner sidewall spacer protects against chamfering during the via etch and/or removal of an etch stop layer over conductive structures in an underlying ILD layer. In one embodiment, a barrier liner is deposited over the metal liner sidewall spacer, creating a double layered sidewall spacer on the sidewalls of the wire trench opening portion of the via-wire opening. A conductor is deposited to form a unitary via-wire conductive structure. An interconnect includes the double layered sidewall spacer on the sidewalls of a wire trench opening portion of the via-wire conductive structure.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Ravi P. Srivastava, Sipeng Gu, Akshey Sehgal