Abstract: A user equipment (UE) may monitor a channel for wireless communication associated with a first radio access technology (RAT) during one or more of a first active duration or a first inactive duration. The UE may operate in a first power mode during the first inactive duration. The UE may monitor the channel for wireless communication associated with a second RAT during one or more of a second active duration or a second inactive duration. The UE may operate during the second inactive duration in one or more of the first power mode or a second power. The UE may operate according to the first mode or the second mode based on the monitoring of the channel associated with the first RAT and the second RAT.

Abstract: Computer-implemented processes for precision therapeutic biomarker screening for cancer include using a model-based overlapping clustering framework to assess large numbers of possible drugs and drug combinations against patient data, including cell line responsiveness. A multivariate regression model has been developed, along with a latent overlapping cluster indicator variable. The techniques employ a new finite mixture of multivariate regression (FMMR) model and expectation-maximization (EM) algorithm for modeling. The techniques can analyze large amounts of drug data and identify complex overlapping drug clusters, as well as cluster-wise drivers that facilitate identification of new drugs for treating pathologies, such as cancer, in patients.

Abstract: Aspects of the subject technology relate to a system configured to receive a set of network snapshot segments from an output stream of a stream processing service, compile the set of network snapshot segments from the set of messages into a first network snapshot and a second network snapshot, and compare the first network snapshot and the second network snapshot to identify a difference between the first network snapshot and the second network snapshot.

Abstract: A system includes a transmitter to transmit a set of bits associated with signaling having one or more levels. The system includes a receiver coupled to the transmitter, the receiver to receive the set of bits and generate a first plurality of digital values, each digital value generated at a first timing value and a plurality of reference voltages, the reference voltage incremented based at least in part on generating a digital value of the first plurality of digital values. The receiver is to generate a second plurality of digital values at a second timing value and the plurality of reference voltages, the first timing value incremented to the second timing value based at least in part on generating the first plurality of digital values. The system includes a controller to determine an amplitude associated with each the first and second plurality of digital values.

Abstract: Various embodiments of a system and associated method for detection of COVID-19 and other respiratory diseases through classification of audio samples are disclosed herein. The system utilizes features directly extracted from the coughing audio and develops automated diagnostic tools for COVID-19. In particular, the present application discusses a novel modification of a deep neural network architecture by using log-mel spectrograms of the audio excerpts and by optimizing a combination of binary cross-entropy and focal loss parameters. One embodiment of the system achieved an average validation AUC of 82.23% and a test AUC of 78.3% at a sensitivity of 80.49%.

Abstract: A system includes a transmitter to transmit a set of bits associated with signaling having one or more levels. The system includes a receiver coupled to the transmitter, the receiver to receive the set of bits and generate a first plurality of digital values, each digital value generated at a first timing value and a plurality of reference voltages, the reference voltage incremented based at least in part on generating a digital value of the first plurality of digital values. The receiver is to generate a second plurality of digital values at a second timing value and the plurality of reference voltages, the first timing value incremented to the second timing value based at least in part on generating the first plurality of digital values. The system includes a controller to determine an amplitude associated with each the first and second plurality of digital values.

Abstract: Various embodiments include a memory device that recovers from write errors and read errors more quickly relative to prior memory devices. Certain patterns of write data and read data may result on poor signal quality on the memory interface between memory controllers and memory devices. The disclosed memory device, synchronously with the memory controller, scrambles read data before transmitting the data to the memory controller and descrambles received from the memory controller. The scrambling and descrambling results in a different pattern on the memory interface even for the same read data or write data. Therefore, when a write operation or a read operation fails, and the operation is replayed, the pattern transmitted on the memory interface is different when the operation is replayed. As a result, the memory device more easily recovers from data patterns that cause poor signal quality on the memory interface.

Abstract: Examples include a computing system including a heater element for heating a processor device installed in the computing system. The computing system includes a chassis, a circuit board assembly housed in the chassis and a heat sink assembly disposed on the chassis to form a cover of the chassis. The circuit board assembly includes a processor package including a substrate having a first portion and a second portion. The processor package includes the processor device disposed on the first portion of the substrate. The heater element disposed on the second portion of the substrate. In the computing system, the heat sink assembly is disposed on the chassis such that a gap separates the heat sink assembly and the heater element.

Abstract: Various embodiments include a memory device that recovers from write errors and read errors more quickly relative to prior memory devices. Certain patterns of write data and read data may result on poor signal quality on the memory interface between memory controllers and memory devices. The disclosed memory device, synchronously with the memory controller, scrambles read data before transmitting the data to the memory controller and descrambles received from the memory controller. The scrambling and descrambling results in a different pattern on the memory interface even for the same read data or write data. Therefore, when a write operation or a read operation fails, and the operation is replayed, the pattern transmitted on the memory interface is different when the operation is replayed. As a result, the memory device more easily recovers from data patterns that cause poor signal quality on the memory interface.

Abstract: Systems, apparatuses, and methods described herein provide heat sinks that can be incorporated into chassis, yet be compatible with edge devices that contain many different combinations of hardware that can be arranged in many different ways on circuit boards. In one example, a pattern of fittings on an interior-facing side of the heat sink are configured to mate with fittings on a first side of an adapter pedestal. A second side of the adapter pedestal is configured to thermally couple with an electronic component housed within the chassis when the heat sink is fully seated and the pedestal is properly coupled to the heat sink.

Abstract: Examples include a computing system including a heater element for heating a processor device installed in the computing system. The computing system includes a chassis, a circuit board assembly housed in the chassis and a heat sink assembly disposed on the chassis to form a cover of the chassis. The circuit board assembly includes a processor package including a substrate having a first portion and a second portion. The processor package includes the processor device disposed on the first portion of the substrate. The heater element disposed on the second portion of the substrate. In the computing system, the heat sink assembly is disposed on the chassis such that a gap separates the heat sink assembly and the heater element.

Abstract: Various embodiments of a system and associated method for detecting and classifying faults in a photovoltaic array using graph-based signal processing.

Abstract: Example implementations relate a chassis for a circuit assembly. The chassis includes a chassis body defining an access opening and a volume to house the circuit assembly including a circuit module and an input-output (IO) unit. The chassis body houses the circuit assembly such that the circuit module is enclosed within the volume defined by the chassis body and the IO unit remains accessible for cabling at the access opening. The chassis further includes an IO enclosure attached to the chassis body to seal the access opening from surrounding environment, where the IO enclosure includes a cabling port to allow the cabling to the IO unit.

Abstract: A method includes receiving medical image data from an image sharing application running on a sharing device. The method further includes determining a category of medical information represented in the medical image data. The method also includes identifying a viewing device to view the medical image data. The method additionally includes transmitting, to the viewing device, a request for confirmation of a medical condition associated with the category of medical information, wherein the request allows the viewing device to view the medical image data in an image viewing application running on the viewing device before an end of a timeout period. The method further includes receiving, from the viewing device, a signal confirming the medical condition based on the medical image data. The method also includes in response to receiving the signal, transmitting an activation signal to each member user device of a medical team associated with the viewing device.

Abstract: Systems, apparatuses, and methods described herein provide heat sinks that can be incorporated into chassis, yet be compatible with edge devices that contain many different combinations of hardware that can be arranged in many different ways on circuit boards. In one example, a pattern of fittings on an interior-facing side of the heat sink are configured to mate with fittings on a first side of an adapter pedestal. A second side of the adapter pedestal is configured to thermally couple with an electronic component housed within the chassis when the heat sink is fully seated and the pedestal is properly coupled to the heat sink.

Abstract: A flexible heat transfer mechanism is provided for transferring heat from a heat generating component to a heatsink. The heat transfer mechanism may include a pedestal coupled to the heatsink via a heat transfer element. The heat transfer element may be a compliant member that is capable of flexing in a vertical direction such that the pedestal may be vertically displaced relative to the heatsink.

Abstract: Example implementations relate a chassis for a circuit assembly. The chassis includes a chassis body defining an access opening and a volume to house the circuit assembly including a circuit module and an input-output (IO) unit. The chassis body houses the circuit assembly such that the circuit module is enclosed within the volume defined by the chassis body and the IO unit remains accessible for cabling at the access opening. The chassis further includes an IO enclosure attached to the chassis body to seal the access opening from surrounding environment, where the IO enclosure includes a cabling port to allow the cabling to the IO unit.

Abstract: Examples relate to a removable transceiver module that comprises a base frame installable in a rail-pair receptacle that surrounds a first connector in a system board. It further comprises a module base board, a second connector attached thereto and a lever handle pivotally attached to the base frame and coupled to the module base board. The transceiver module is installed in the rail-pair receptacle in response to a lateral movement of the base frame to the receptacle to align the first and second connectors. The lever handle is movable between a closed position to couple the second connector to the first connector and an open position to install the transceiver module into the receptacle. This lever handle determines a vertical move of the module base board between the closed position and the open position.

Abstract: Systems and methods for mounting a computing device. One system includes a wall mounting bracket having a front side and a back side. The system further includes a main chassis having a front side panel removably connected to the front side of the wall mounting bracket, a second side panel removably connected to the front side of the wall mounting bracket, and a computing device having a first side and a second side, the first side removably attached to the first side panel and the second side removably attached to the second side panel, and the main chassis connected to the front side of the wall mounting bracket.

Abstract: Systems and methods for mounting a computing device. One system includes a wall mounting bracket having a front side and a back side. The system further includes a main chassis having a front side panel removably connected to the front side of the wall mounting bracket, a second side panel removably connected to the front side of the wall mounting bracket, and a computing device having a first side and a second side, the first side removably attached to the first side panel and the second side removably attached to the second side panel, and the main chassis connected to the front side of the wall mounting bracket.